NXP Semiconductors LPC24XX UM10237 - Manual (Page 93)

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User manual Rev. 04 — 26 August 2009 93 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
[1] Extended wait and page mode cannot be selected simultaneously.
[2] EMC may perform burst read access even when the buffer enable bit is cleared.
10.22 Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 -
0xFFE0 8204, 224, 244 ,264)
The EMCStaticWaitWen0-3 registers enable you to program the delay from the chip select
to the write enable. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
7 Byte lane state
(PB) The byte lane state bit, PB, enables different types of
memory to be connected. For byte-wide static memories
the BLSn[3:0] signal from the EMC is usually connected
to WE (write enable). In this case for reads all the
BLSn[3:0] bits must be HIGH. This means that the byte
lane state (PB) bit must be LOW.
16 bit wide static memory devices usually have the
BLSn[3:0] signals connected to the UBn and LBn (upper
byte and lower byte) signals in the static memory. In this
case a write to a particular byte must assert the
appropriate UBn or LBn signal LOW. For reads, all the
UB and LB signals must be asserted LOW so that the
bus is driven. In this case the byte lane state (PB) bit
must be HIGH.
0
0 For reads all the bits in BLSn[3:0] are HIGH. For writes
the respective active bits in BLSn[3:0] are LOW (POR
reset value).
1 For reads the respective active bits in BLSn[3:0] are
LOW. For writes the respective active bits in BLSn[3:0]
are LOW.
8 Extended wait
(EW) Extended wait (EW) uses the EMCStaticExtendedWait
register to time both the read and write transfers rather
than the EMCStaticWaitRd and EMCStaticWaitWr
registers. This enables much longer transactions.
[1]
0
0 Extended wait disabled (POR reset value).
1 Extended wait enabled.
18:9 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
19 Buffer enable [2]
(B)
0 Buffer disabled (POR reset value). 0
1 Buffer enabled.
20 Write protect (P) 0 Writes not protected (POR reset value). 0
1 Write protected.
31:21 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA
Table 89. Static Memory Configuration registers (EMCStaticConfig0-3 - address
0xFFE0 8200, 0xFFE0 8220, 0xFFE0 8240, 0xFFE0 8260) bit description
Bit Symbol Value Description Reset
Value