NXP Semiconductors LPC24XX UM10237 - Manual (Page 273)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 273 of 792
NXP Semiconductors
UM10237
Chapter 11: LPC24XX Ethernet
After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is
set in the Command register, the state machine transitions to the ACTIVE state. As soon
as the RxEnable bit is cleared, the state machine returns to the INACTIVE state. If the
receive datapath is busy receiving a packet while the receive datapath gets disabled, the
packet will be received completely, stored to memory along with its status before returning
to the INACTIVE state. Also if the Receive descriptor array is full, the state machine will
return to the INACTIVE state.
For the state machine in Figure 11–34 , a soft reset is like a hardware reset assertion, i.e.
after a soft reset the receive datapath is inactive until the datapath is re-enabled.
Enabling and disabling transmission
After reset, the transmit function of the Ethernet block is disabled. The Tx transmit
datapath can be enabled by the device driver setting the TxEnable bit in the Command
register to 1.
The status of the transmit datapaths can be monitored by the device driver reading the
TxStatus bit of the Status register.
Figure 11–35 illustrates the state machine for the
generation of the TxStatus bit.
Fig 34. Receive Active/Inactive state machine
ACTIVE
RxStatus = 1
INACTIVE
RxStatus = 0
RxEnable = 1
RxEnable = 0 and not busy receiving
OR
RxProduceIndex = RxConsumeIndex - 1
reset
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