NXP Semiconductors LPC24XX UM10237 - Manual (Page 258)

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User manual Rev. 04 — 26 August 2009 258 of 792
NXP Semiconductors
UM10237
Chapter 11: LPC24XX Ethernet
Since the Interrupt bit in the descriptor of the last fragment is set, after committing the
status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt,
which triggers the device driver to inspect the status information.
In this example the device driver cannot add new descriptors as long as the Ethernet
block has not incremented the TxConsumeIndex because the descriptor array is full (even
though one descriptor is not programmed yet). Only after the hardware commits the status
for the first fragment to memory and the TxConsumeIndex is set to 1 by the DMA manager
can the device driver program the next (the fourth) descriptor. The fourth descriptor can
already be programmed before completely transmitting the first frame.
In this example the hardware adds the CRC to the frame. If the device driver software
adds the CRC, the CRC trailer can be considered another frame fragment which can be
added by doing another gather DMA.
Each data byte is transmitted across the MII interface as two nibbles. On the MII interface
the Ethernet block adds the preamble, frame delimiter leader, and the CRC trailer if
hardware CRC is enabled. Once transmission on the MII interface commences the
transmission cannot be interrupted without generating an underrun error, which is why
descriptors and data read commands are issued as soon as possible and pipelined.
For an RMII PHY, the data communication between the Ethernet block and the PHY is
communicated at half the data-width (2 bits) and twice the clock frequency (50 MHz). In
10 Mbps mode data will only be transmitted once every 10 clock cycles.
9.7 Receive process
This section outlines the receive process including the activities in the device driver
software.
Device driver sets up descriptors
After initializing the receive descriptor and status arrays to receive frames from the
Ethernet connection, the receive datapath should be enabled in the MAC1 register and
the Control register.
During initialization, each Packet pointer in the descriptors is set to point to a data
fragment buffer. The size of the buffer is stored in the Size bits of the Control field of the
descriptor. Additionally, the Control field in the descriptor has an Interrupt bit. The Interrupt
bit allows generation of an interrupt after a fragment buffer has been filled and its status
has been committed to memory.
After the initialization and enabling of the receive datapath, all descriptors are owned by
the receive hardware and should not be modified by the software unless hardware hands
over the descriptor by incrementing the RxProduceIndex, indicating that a frame has been
received. The device driver is allowed to modify the descriptors after a (soft) reset of the
receive datapath.
Rx DMA manager reads Rx descriptor arrays
When the RxEnable bit in the Command register is set, the Rx DMA manager reads the
descriptors from memory at the address determined by RxDescriptor and
RxProduceIndex. The Ethernet block will start reading descriptors even before actual
receive data arrives on the (R)MII interface (descriptor prefetching). The block size of the