NXP Semiconductors LPC24XX UM10237 - Manual (Page 770)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 770 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
addresses 0xE001 C018, 0xE005 C018,
0xE008 0018) bit description . . . . . . . . . . . . .584
Table 515.I 2 C Status Register (I2C[0/1/2]STAT - addresses
0xE001 C004, 0xE005 C004, 0xE008 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .584
Table 516.I 2 C Data Register ( I2C[0/1/2]DAT - addresses
0xE001 C008, 0xE005 C008, 0xE008 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .585
Table 517.I 2 C Slave Address register (I2C[0/1/2]ADR -
addresses 0xE001 C00C, 0xE005 C00C,
0xE008 000C) bit description . . . . . . . . . . . . .585
Table 518.I 2 C SCL High Duty Cycle register
(I2C[0/1/2]SCLH - addresses 0xE001 C010,
0xE005 C010, 0xE008 0010) bit description .585
Table 519.I 2 C SCL Low Duty Cycle register (I2C[0/1/2]SCLL
- addresses 0xE001 C014, 0xE005 C014,
0xE008 0014) bit description . . . . . . . . . . . . .585
Table 520.Example I 2 C Clock Rates . . . . . . . . . . . . . . . .586
Table 521.Abbreviations used to describe an I 2 C
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .586
Table 522.I2CONSET used to initialize Master Transmitter
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
Table 523.I2C0ADR and I2C1ADR usage in Slave Receiver
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .588
Table 524.I2C0CONSET and I2C1CONSET used to initialize
Slave Receiver mode . . . . . . . . . . . . . . . . . . .588
Table 525.Master Transmitter mode . . . . . . . . . . . . . . . .594
Table 526.Master Receiver mode . . . . . . . . . . . . . . . . . .595
Table 527.Slave Receiver Mode . . . . . . . . . . . . . . . . . . .596
Table 528.Tad_105: Slave Transmitter mode . . . . . . . . .598
Table 529.Miscellaneous states . . . . . . . . . . . . . . . . . . .600
Table 530.Pin descriptions . . . . . . . . . . . . . . . . . . . . . . .612
Table 531.Summary of I2S registers . . . . . . . . . . . . . . . .613
Table 532:Digital Audio Output register (I2SDAO - address
0xE008 8000) bit description . . . . . . . . . . . . .614
Table 533:Digital Audio Input register (I2SDAI - address
0xE008 8004) bit description . . . . . . . . . . . . .615
Table 534:Transmit FIFO register (I2STXFIFO - address
0xE008 8008) bit description . . . . . . . . . . . . .615
Table 535:Receive FIFO register (I2RXFIFO - address
0xE008 800C) bit description . . . . . . . . . . . . .615
Table 536:Status Feedback register (I2SSTATE - address
0xE008 8010) bit description . . . . . . . . . . . . .615
Table 537:DMA Configuration register 1 (I2SDMA1 - address
0xE008 8014) bit description . . . . . . . . . . . . .616
Table 538:DMA Configuration register 2 (I2SDMA2 - address
0xE008 8018) bit description . . . . . . . . . . . . .616
Table 539:Interrupt Request Control register (I2SIRQ -
address 0xE008 801C) bit description . . . . . .617
Table 540:Transmit Clock Rate register (I2TXRATE -
address 0xE008 8020) bit description . . . . . .617
Table 541:Receive Clock Rate register (I2SRXRATE -
address 0xE008 8024) bit description . . . . . .617
Table 542.Conditions for FIFO level comparison . . . . . .619
Table 543.DMA and interrupt request generation . . . . . .619
Table 544.Status feedback in the I2SSTATE register . . .619
Table 545.Timer/Counter pin description. . . . . . . . . . . . .622
Table 546.Summary of timer/counter registers . . . . . . . .623
Table 547:Interrupt Register (T[0/1/2/3]IR - addresses
0xE000 4000, 0xE000 8000, 0xE007 0000,
0xE007 4000) bit description . . . . . . . . . . . . . 624
Table 548:Timer Control Register (TCR, TIMERn: TnTCR -
addresses 0xE000 4004, 0xE000 8004,
0xE007 0004, 0xE007 4004) bit description . 625
Table 549:Count Control Register (T[0/1/2/3]CTCR -
addresses 0xE000 4070, 0xE000 8070,
0xE007 0070, 0xE007 4070) bit description . 625
Table 550:Match Control Register (T[0/1/2/3]MCR -
addresses 0xE000 4014, 0xE000 8014,
0xE007 0014, 0xE007 4014) bit description . 627
Table 551:Capture Control Register (T[0/1/2/3]CCR -
addresses 0xE000 4028, 0xE000 8020,
0xE007 0028, 0xE007 4028) bit description . 628
Table 552:External Match Register (T[0/1/2/3]EMR -
addresses 0xE000 403C, 0xE000 803C,
0xE007 003C, 0xE007 403C) bit description . 629
Table 553.External Match Control . . . . . . . . . . . . . . . . . 629
Table 554.Set and reset inputs for PWM flip-flops . . . . . 637
Table 555.Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 637
Table 556:Addresses for PWM 0 and 1 . . . . . . . . . . . . . 637
Table 557.PWM0 and PWM1 register map . . . . . . . . . . 638
Table 558:PWM Interrupt Register (PWM0IR - address
0xE001 4000 and PWM1IR address
0xE001 8000) bit description . . . . . . . . . . . . . 639
Table 559:PWM Timer Control Register (PWM0TCR -
address 0xE001 4004 PWM1TCR address
0xE001 8004) bit description . . . . . . . . . . . . . 640
Table 560:PWM Count control Register (PWM0TCR -
address 0xE001 4004 and PWM1CTCR address
0xE001 8004) bit description . . . . . . . . . . . . . 641
Table 561:Match Control Register (PWM0MCR - address
0xE000 4014 and PWM1MCR - address
0xE000 8014) bit description . . . . . . . . . . . . . 641
Table 562:PWM Capture Control Register (PWM0CCR -
address 0xE001 4028 and PWM1CCR address
0xE001 8028) bit description . . . . . . . . . . . . . 643
Table 563:PWM Control Registers (PWMPCR - address
0xE001 404C and PWM1PCR address
0xE001 804C) bit description. . . . . . . . . . . . . 644
Table 564:PWM Latch Enable Register (PWM0LER -
address 0xE001 4050 and PWM1LER address
0xE001 8050) bit description . . . . . . . . . . . . . 645
Table 565.RTC pin description . . . . . . . . . . . . . . . . . . . . 648
Table 566.Summary of Real-Time Clock registers . . . . 649
Table 567.Interrupt Location Register (ILR - address
0xE002 4000) bit description . . . . . . . . . . . . . 650
Table 568.Clock Tick Counter Register (CTCR - address
0xE002 4004) bit description . . . . . . . . . . . . . 651
Table 569.Clock Control Register (CCR - address
0xE002 4008) bit description . . . . . . . . . . . . . 651
Table 570.Counter Increment Interrupt Register (CIIR -
address 0xE002 400C) bit description . . . . . . 652
Table 571.Counter Increment Select Mask register (CISS -
address 0xE002 4040) bit description . . . . . . 652
Table 572.Alarm Mask Register (AMR - address
0xE002 4010) bit description . . . . . . . . . . . . . 653