NXP Semiconductors LPC24XX UM10237 - Manual (Page 211)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 211 of 792
1. How to read this chapter
The Ethernet controller is avialable in parts LPC2458 and LPC2460/68/70/78.
2. Basic configuration
The Ethernet controller is configured using the following registers:
1. Power: In the PCONP register ( Table 4–63 ), set bit PCENET.
Remark: On reset, the Ethernet block is disabled (PCENET = 0).
2. Clock: see Section 4–3.3.1 .
3. Pins: Select Ethernet pins and their modes in PINSEL2/3 and PINMODE2/3
( Section 9–5 ).
4. Wakeup: Use the INTWAKE register ( Section 4–3.4.8 ) to enable activity on the
Ethernet port to wake up the microcontroller from Power-down mode.
5. Interrupts: Interrupts are enabled in the VIC using the VICIntEnable register
( Section 7–3.4 ).
6. Initialization: see Section 11–9.5 .
3. Introduction
The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media
Access Controller) designed to provide optimized performance through the use of DMA
hardware acceleration. Features include a generous suite of control registers, half or full
duplex operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission and
reception with Scatter-Gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share a dedicated AHB subsystem (AHB2) that is used
to access the Ethernet SRAM for Ethernet data, control, and status information. All other
AHB traffic in the LPC2400 takes place on a different AHB subsystem, effectively
separating Ethernet activity from the rest of the system. The Ethernet DMA can also
access off-chip memory via the External Memory Controller, as well as the SRAM located
on AHB1, if is not being used by the USB block. However, using memory other than the
Ethernet SRAM, especially off-chip memory, will slow Ethernet access to memory and
increase the loading of AHB1.
The Ethernet block interfaces between an off-chip Ethernet PHY using the MII (Media
Independent Interface) or RMII (reduced MII) protocol. and the on-chip MIIM (Media
Independent Interface Management) serial bus.
UM10237
Chapter 11: LPC24XX Ethernet
Rev. 04 — 26 August 2009 User manual