NXP Semiconductors LPC24XX UM10237 - Manual (Page 769)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 769 of 792
NXP Semiconductors
UM10237
Chapter 36: LPC24XX Supplementary information
(FCANIC0 - address 0xE003 C024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .505
Table 453.FullCAN Interrupt and Capture register 1
(FCANIC1 - address 0xE003 C028)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .505
Table 454.Format of automatically stored Rx messages.509
Table 455.FullCAN semaphore operation . . . . . . . . . . . .509
Table 456.Example of Acceptance Filter Tables and ID index
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .519
Table 457.Used ID-Look-up Table sections. . . . . . . . . . .521
Table 458.Used ID-Look-up Table sections. . . . . . . . . . .522
Table 459.SPI Data To Clock Phase Relationship. . . . . .527
Table 460.SPI pin description . . . . . . . . . . . . . . . . . . . . .530
Table 461.SPI register map . . . . . . . . . . . . . . . . . . . . . . .531
Table 462:SPI Control Register (S0SPCR - address
0xE002 0000) bit description . . . . . . . . . . . . .531
Table 463:SPI Status Register (S0SPSR - address
0xE002 0004) bit description . . . . . . . . . . . . .532
Table 464:SPI Data Register (S0SPDR - address
0xE002 0008) bit description . . . . . . . . . . . . .533
Table 465:SPI Clock Counter Register (S0SPCCR - address
0xE002 000C) bit description . . . . . . . . . . . . .533
Table 466:SPI Test Control Register (SPTCR - address
0xE002 0010) bit description . . . . . . . . . . . . .534
Table 467:SPI Test Status Register (SPTSR - address
0xE002 0014) bit description . . . . . . . . . . . . .534
Table 468:SPI Interrupt Register (S0SPINT - address
0xE002 001C) bit description . . . . . . . . . . . . .534
Table 469.SSP pin descriptions . . . . . . . . . . . . . . . . . . .537
Table 470.SSP Register Map . . . . . . . . . . . . . . . . . . . . .545
Table 471:SSPn Control Register 0 (SSP0CR0 - address
0xE006 8000, SSP1CR0 - 0xE003 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .546
Table 472:SSPn Control Register 1 (SSP0CR1 - address
0xE006 8004, SSP1CR1 - 0xE003 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .547
Table 473:SSPn Data Register (SSP0DR - address
0xE006 8008, SSP1DR - 0xE003 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .547
Table 474:SSPn Status Register (SSP0SR - address
0xE006 800C, SSP1SR - 0xE003 000C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .548
Table 475:SSPn Clock Prescale Register (SSP0CPSR -
address 0xE006 8010, SSP1CPSR -
0xE003 8010) bit description . . . . . . . . . . . . .548
Table 476:SSPn Interrupt Mask Set/Clear register
(SSP0IMSC - address 0xE006 8014, SSP1IMSC
- 0xE003 0014) bit description . . . . . . . . . . . .549
Table 477:SSPn Raw Interrupt Status register (SSP0RIS -
address 0xE006 8018, SSP1RIS - 0xE003 0018)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .549
Table 478:SSPn Masked Interrupt Status register (SSPnMIS
-address 0xE006 801C, SSP1MIS -
0xE003 001C) bit description . . . . . . . . . . . . .550
Table 479:SSPn interrupt Clear Register (SSP0ICR -
address 0xE006 8020, SSP1ICR - 0xE003 0020)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .550
Table 480:SSPn DMA Control Register (SSP0DMACR -
address 0xE006 8024, SSP1DMACR -
0xE003 0024) bit description . . . . . . . . . . . . . 550
Table 481.SD/MMC card interface pin description . . . . . 551
Table 482.Command format . . . . . . . . . . . . . . . . . . . . . . 556
Table 483.Simple response format . . . . . . . . . . . . . . . . . 556
Table 484.Long response format . . . . . . . . . . . . . . . . . . 556
Table 485.Command path status flags . . . . . . . . . . . . . . 557
Table 486.CRC token status . . . . . . . . . . . . . . . . . . . . . . 560
Table 487.Data path status flags . . . . . . . . . . . . . . . . . . 561
Table 488.Transmit FIFO status flags. . . . . . . . . . . . . . . 562
Table 489.Receive FIFO status flags . . . . . . . . . . . . . . . 563
Table 490.Summary of MCI registers . . . . . . . . . . . . . . . 563
Table 491:Power Control register (MCIPower - address
0xE008 C000) bit description. . . . . . . . . . . . . 564
Table 492:Clock Control register (MCIClock - address
0xE008 C004) bit description. . . . . . . . . . . . . 565
Table 493:Argument register (MCIArgument - address
0xE008 C008) bit description. . . . . . . . . . . . . 565
Table 494:Command register (MCICommand - address
0xE008 C00C) bit description . . . . . . . . . . . . 566
Table 495:Command Response Types. . . . . . . . . . . . . . 566
Table 496:Command Response register
(MCIRespCommand - address 0xE008 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
Table 497:Response registers (MCIResponse0-3 -
addresses 0xE008 0014, 0xE008 C018,
0xE008 001C and 0xE008 C020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
Table 498:Response Register Type . . . . . . . . . . . . . . . . 567
Table 499:Data Timer register (MCIDataTimer - address
0xE008 C024) bit description. . . . . . . . . . . . . 567
Table 500:Data Length register (MCIDataLength - address
0xE008 C028) bit description. . . . . . . . . . . . . 567
Table 501:Data Control register (MCIDataCtrl - address
0xE008 C02C) bit description . . . . . . . . . . . . 568
Table 502:Data Block Length . . . . . . . . . . . . . . . . . . . . . 568
Table 503:Data Counter register (MCIDataCnt - address
0xE008 C030) bit description. . . . . . . . . . . . . 569
Table 504:Status register (MCIStatus - address
0xE008 C034) bit description. . . . . . . . . . . . . 569
Table 505:Clear register (MCIClear - address 0xE008 C038)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 570
Table 506:Interrupt Mask registers (MCIMask0 - address
0xE008 C03C) bit description . . . . . . . . . . . . 570
Table 507:FIFO Counter register (MCIFifoCnt - address
0xE008 C048) bit description. . . . . . . . . . . . . 571
Table 508:Data FIFO register (MCIFIFO - address
0xE008 C080 to 0xE008 C0BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
Table 509.I 2 C Pin Description. . . . . . . . . . . . . . . . . . . . . 574
Table 510.I2CnCONSET used to configure Master
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
Table 511. I2CnCONSET used to configure Slave mode 576
Table 512.Summary of I
2 C registers. . . . . . . . . . . . . . . . 581
Table 513.I 2 C Control Set Register (I2C[0/1/2]CONSET -
addresses: 0xE001 C000, 0xE005 C000,
0xE008 0000) bit description . . . . . . . . . . . . . 582
Table 514.I 2 C Control Set Register (I2C[0/1/2]CONCLR -