NXP Semiconductors LPC24XX UM10237 - Manual (Page 395)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 395 of 792
NXP Semiconductors
UM10237
Chapter 15: LPC24XX USB OTG controller
support an OTG connection. The communication between the register interface and an
external OTG transceiver is handled through an I
2 C interface and through the external
OTG transceiver interrupt signal.
For USB connections that use the device or host controller only (not OTG), the ports use
an embedded USB Analog Transceiver (ATX).
5. Modes of operation
The OTG controller is capable of operating in the following modes:
• One port host and one port dual-role device (see Figure 15–53 )
• One port host and one port device (see Figure 15–55 )
• Two-port host (see Figure 15–56 )
6. Pin configuration
The OTG controller has two USB ports indicated by suffixes 1 and 2 in the USB pin names
and referred to as USB port 1 (U1) and USB port 2 (U2) in the following text.
Fig 52. USB OTG controller block diagram
REGISTER
INTERFACE
BUS
MASTER
INTERFACE
USB
ATX
USB
ATX
DMA interface
(AHB master)
register
interface
(AHB slave)
AHB b
u
s
I2C
CONTROLLER
DEVICE
CONTROLLER
HOST
CONTROLLER
EP_RAM
OTG
CONTROLLER
ATX
CONTROL
LOGIC/
PORT
MUX
port 1
port 1
port 2
U2
port
U1
port
OTG
TRANSCEIVER
USB OTG BLOCK