NXP Semiconductors LPC24XX UM10237 - Manual (Page 281)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 281 of 792
1. How to read this chapter
The LCD controller is available on parts LPC2470 and LPC2478 only.
2. Basic configuration
The LCD controller is configured using the following registers:
1. Power: In the PCONP register ( Table 4–63 ), set bit PCLCD.
Remark: The LCD is disabled on reset (PCLCD = 0).
Also see Section 12–6.12 for power-up procedure.
2. Clock: see Table 4–53 , Table 12–263 , and Table 12–260 .
3. Pins: Enable the LCD controller port using the PINSEL11 register ( Table 9–145 ) and
select individual LCD pins using PINSEL0 ( Table 9–130 ), PINSEL3 ( Table 9–133 ),
PINSEL4 ( Table 9–135 ), and PINSEL9 ( Table 9–143 ).
4. Configuration: see Table 9–145 .
3. Introduction
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels.
4. Features
• AHB bus master interface to access frame buffer.
• Setup and control via a separate AHB slave interface.
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4 or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320x200, 320x240,
640x200, 640x240, 640x480, 800x600, and 1024x768.
• Hardware cursor support for single-panel displays.
• 15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support.
• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
• 16 bpp true-color non-palettized, for color STN and TFT.
• 24 bpp true-color non-palettized, for color TFT.
• Programmable timing for different display panels.
UM10237
Chapter 12: LPC24XX LCD controller
Rev. 04 — 26 August 2009 User manual