NXP Semiconductors LPC24XX UM10237 - Manual (Page 402)

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User manual Rev. 04 — 26 August 2009 402 of 792
NXP Semiconductors
UM10237
Chapter 15: LPC24XX USB OTG controller
7.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100)
Bits is this register are set by hardware when the interrupt event occurs during the HNP
handoff sequence. See
Section 15–8 for more information on when these bits are set.
7.3 OTG Interrupt Enable Register (OTGIntEn - 0xFFE0 C104)
Writing a one to a bit in this register enables the corresponding bit in OTGIntSt to generate
an interrupt on one of the interrupt lines. The interrupt is routed to the USB_OTG_INT
interrupt line in the USBIntSt register.
The bit allocation and reset value of OTGIntEn is the same as OTGIntSt.
7.4 OTG Interrupt Set Register (OTGIntSet - 0xFFE0 C20C)
Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.
Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.
7.5 OTG Interrupt Clear Register (OTGIntClr - 0xFFE0 C10C)
Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt
register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in
OTGIntSt.
7.6 OTG Status and Control Register (OTGStCtrl - 0xFFE0 C110)
The OTGStCtrl register allows enabling hardware tracking during the HNP hand over
sequence, controlling the OTG timer, monitoring the timer count, and controlling the
functions mapped to port U1 and U2.
Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:
1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section
15–7.7 “OTG Timer Register (OTGTmr - 0xFFE0 C114)” ), the TMR bit is set in
OTGIntSt, and the timer will be disabled.
Table 364. OTG Interrupt Status register (OTGIntSt - address 0xE01F C100) bit description
Bit Symbol Description Reset
Value
0 TMR Timer time-out. 0
1 REMOVE_PU Remove pull-up.
This bit is set by hardware to indicate that software
needs to disable the D+ pull-up resistor.
0
2 HNP_FAILURE HNP failed.
This bit is set by hardware to indicate that the HNP
switching has failed.
0
3 HNP_SUCCESS HNP succeeded.
This bit is set by hardware to indicate that the HNP
switching has succeeded.
0
31:4 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined. NA