NXP Semiconductors LPC24XX UM10237 - Manual (Page 731)

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User manual Rev. 04 — 26 August 2009 731 of 792
NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
6.2.6 Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110 and
DMACC1Configuration - 0xFFE0 4130)
The two DMACCxConfiguration Registers are read/write with the exception of bit[17]
which is read-only. Used these to configure the DMA channel. The registers are not
updated when a new LLI is requested.
Table 32–674 shows the bit assignments of the
DMACCxConfiguration Register.
30 Cacheable or not cacheable. This indicates that the access is
cacheable. This bit can, for example, be used to indicate to an
AMBA bridge that when it saw the first read of a burst of eight it
can transfer the whole burst of eight reads on the destination
bus, rather than pass the transactions through one at a time.
This bit controls the AHB HPROT[3] signal.
Indicates that the access is cacheable or not cacheable:
0
0 Not cacheable.
1 Cacheable.
Table 673. Protection bits
DMACC1Control
Bit Value Description Reset
Value
Table 674. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and
DMACC1Configuration - address 0xFFE0 4130) bit description
Bit Symbol Value Description Reset
Value
0 E The Channel Enable bit status can also be found by reading the DMACEnbldChns
Register.
A channel is enabled by setting this bit.
A channel can be disabled by clearing the Enable bit. This causes the current AHB
transfer (if one is in progress) to complete and the channel is then disabled. Any
data in the FIFO of the relevant channel is lost. Restarting the channel by setting the
Channel Enable bit has unpredictable effects and the channel must be fully
re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the last LLI is
reached or if a channel error is encountered.
If a channel has to be disabled without losing data in the FIFO the Halt bit must be
set so that further DMA requests are ignored. The Active bit must then be polled
until it reaches 0, indicating that there is no data left in the FIFO. Finally the Channel
Enable bit can be cleared.
Channel enable -- reading this bit indicates whether a channel is currently enabled
or disabled:
0
0 Channel disabled.
1 Channel enabled.