NXP Semiconductors LPC24XX UM10237 - Manual (Page 645)

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User manual Rev. 04 — 26 August 2009 645 of 792
NXP Semiconductors
UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
6.7 PWM Latch Enable Register (PWM0LER - 0xE001 4050 and PWM1LER
0xE001 8050)
The PWM Latch Enable registers are used to control the update of the PWM Match
registers when they are used for PWM generation. When software writes to the location of
a PWM Match register while the Timer is in PWM mode, the value is actually held in a
shadow register and not used immediately.
When a PWM Match 0 event occurs (normally also resetting the timer in PWM mode), the
contents of shadow registers will be transferred to the actual Match registers if the
corresponding bit in the Latch Enable register has been set. At that point, the new values
will take effect and determine the course of the next PWM cycle. Once the transfer of new
values has taken place, all bits of the LER are automatically cleared. Until the
corresponding bit in the PWMLER is set and a PWM Match 0 event occurs, any value
written to the PWM Match registers has no effect on PWM operation.
For example, if PWM is configured for double edge operation and is currently running, a
typical sequence of events for changing the timing would be:
• Write a new value to the PWM Match1 register.
• Write a new value to the PWM Match2 register.
• Write to the PWMLER, setting bits 1 and 2 at the same time.
• The altered values will become effective at the next reset of the timer (when a PWM
Match 0 event occurs).
The order of writing the two PWM Match registers is not important, since neither value will
be used until after the write to PWMLER. This insures that both values go into effect at the
same time, if that is required. A single value may be altered in the same way if needed.
The function of each of the bits in the PWMLER is shown in Table 25–564 .
Table 564: PWM Latch Enable Register (PWM0LER - address 0xE001 4050 and PWM1LER
address 0xE001 8050) bit description
Bit Symbol Description Reset
Value
0 Enable PWM
Match 0 Latch PWM MR0 register update control. Writing a one to this bit allows
the last value written to the PWM Match Register 0 to be become
effective when the timer is next reset by a PWM Match event. See
Section 25–6.4 “PWM Match Control Register (PWM0MCR -
0xE001 4014 and PWM1MCR 0xE001 8014)”
.
0
1 Enable PWM
Match 1 Latch PWM MR1 register update control. See bit 0 for details. 0
2 Enable PWM
Match 2 Latch PWM MR2 register update control. See bit 0 for details. 0
3 Enable PWM
Match 3 Latch PWM MR3 register update control. See bit 0 for details. 0
4 Enable PWM
Match 4 Latch PWM MR4 register update control. See bit 0 for details. 0