NXP Semiconductors LPC24XX UM10237 - Manual (Page 390)

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User manual Rev. 04 — 26 August 2009 390 of 792
NXP Semiconductors
UM10237
Chapter 14: LPC24XX USB Host controller
• OpenHCI specifies the operation and interface of the USB Host Controller and SW
Driver
– USBOperational: Process Lists and generate SOF Tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wakeup activity.
– USBResume: Forces resume signaling on the bus.
• The Host Controller has four USB states visible to the SW Driver.
• HCCA register points to Interrupt and Isochronous Descriptors List.
• ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.
2.2 Architecture
The architecture of the USB host controller is shown below in Figure 14–51 .
3. Interfaces
The OTG controller has two USB ports indicated by suffixes 1 and 2 in the USB pin names
and referred to as USB port 1 (U1) and USB port 2 (U2) in the following text.
3.1 Pin description
Fig 51. USB Host controller block diagram
REGISTER
INTERFACE
BUS
MASTER
INTERFACE
USB
ATX
USB
ATX
DMA interface
(AHB master)
register
interface
(AHB slave)
AHB b
u
s HOST
CONTROLLER
ATX
CONTROL
LOGIC/
PORT
MUX
port 1
port 2
U2
port
U1
port
USB HOST BLOCK
Table 359. USB OTG port pins
Pin name Direction Description Pin category
V
BUS
I V
BUS
status input. When this function is not enabled
via its corresponding PINSEL register, it is driven
HIGH internally.
USB Connector
Port U1
USB_D+1 I/O Positive differential data USB Connector
USB_D
−1
I/O Negative differential data USB Connector
USB_CONNECT1 O SoftConnect control signal Control
USB_UP_LED1 O GoodLink LED control signal Control