Table 17–405, Table 17–404, This – NXP Semiconductors LPC24XX UM10237 User Manual

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UM10237_4

© NXP B.V. 2009. All rights reserved.

User manual

Rev. 04 — 26 August 2009

452 of 792

NXP Semiconductors

UM10237

Chapter 17: LPC24XX UART1

It is the lowest priority interrupt and is activated whenever there is any state change on
modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem
input RI will generate a modem interrupt. The source of the modem interrupt can be
determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt.

4.6 UART1 FIFO Control Register (U1FCR - 0xE001 0008, Write Only)

The U1FCR controls the operation of the UART1 RX and TX FIFOs.

4.7 UART1 Line Control Register (U1LCR - 0xE001 000C)

The U1LCR determines the format of the data character that is to be transmitted or
received.

Table 404. UART1 FIFO Control Register (U1FCR - address 0xE001 0008, Write Only) bit

description

Bit

Symbol

Value Description

Reset
Value

0

FIFO
Enable

0

UART1 FIFOs are disabled. Must not be used in the application.

0

1

Active high enable for both UART1 Rx and TX FIFOs and
U1FCR[7:1] access. This bit must be set for proper UART1
operation. Any transition on this bit will automatically clear the
UART1 FIFOs.

1

RX FIFO
Reset

0

No impact on either of UART1 FIFOs.

0

1

Writing a logic 1 to U1FCR[1] will clear all bytes in UART1 Rx
FIFO and reset the pointer logic. This bit is self-clearing.

2

TX FIFO
Reset

0

No impact on either of UART1 FIFOs.

0

1

Writing a logic 1 to U1FCR[2] will clear all bytes in UART1 TX
FIFO and reset the pointer logic. This bit is self-clearing.

5:3

-

Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.

NA

7:6

RX
Trigger
Level

00

These two bits determine how many receiver UART1 FIFO
characters must be written before an interrupt is activated.

0

Trigger level 0 (1 character or 0x01).

01

Trigger level 1 (4 characters or 0x04).

10

Trigger level 2 (8 characters or 0x08).

11

Trigger level 3 (14 characters or 0x0E).

Table 405. UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description

Bit

Symbol Value Description

Reset
Value

1:0

Word
Length
Select

00

5 bit character length.

0

01

6 bit character length.

10

7 bit character length.

11

8 bit character length.

2

Stop Bit
Select

0

1 stop bit.

0

1

2 stop bits (1.5 if U1LCR[1:0]=00).

3

Parity
Enable

0

Disable parity generation and checking.

0

1

Enable parity generation and checking.

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