NXP Semiconductors LPC24XX UM10237 - Manual (Page 71)

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User manual Rev. 04 — 26 August 2009 71 of 792
NXP Semiconductors
UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
5.2 AHB slave memory interface
The AHB slave memory interface allows access to external memories.
5.2.1 Memory transaction endianness
The endianness of the data transfers to and from the external memories is determined by
the Endian mode (N) bit in the EMCConfig register.
Note: The memory controller must be idle (see the busy field of the EMCStatus Register)
before endianness is changed, so that the data is transferred correctly.
5.2.2 Memory transaction size
Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size
greater than a word (32 bits) causes an ERROR response to the AHB bus and the transfer
is terminated.
5.2.3 Write protected memory areas
Write transactions to write-protected memory areas generate an ERROR response to the
AHB bus and the transfer is terminated.
5.3 Pad interface
The pad interface block provides the interface to the pads. The pad interface uses
feedback clocks, FBCLKIN[3:0], to resynchronize SDRAM read data from the off-chip to
on-chip domains.
5.4 Data buffers
The AHB interface reads and writes via buffers to improve memory bandwidth and reduce
transaction latency. The EMC contains four 16-word buffers. The buffers can be used as
read buffers, write buffers, or a combination of both. The buffers are allocated
automatically.
The buffers must be disabled during SDRAM and SyncFlash initialization. They must also
be disabled when performing SyncFlash commands. The buffers must be enabled during
normal operation.
The buffers can be enabled or disabled for static memory using the EMCStaticConfig
Registers.
5.4.1 Write buffers
Write buffers are used to:
• Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
Convert all dynamic memory write transactions into quadword bursts on the external
memory interface. This enhances transfer efficiency for dynamic memory.
• Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Write buffer operation: