NXP Semiconductors LPC24XX UM10237 - Manual (Page 433)

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User manual Rev. 04 — 26 August 2009 433 of 792
NXP Semiconductors
UM10237
Chapter 16: LPC24XX UART0/2/3
2 Parity Error
(PE)
0
When the parity bit of a received character is in the wrong
state, a parity error occurs. An UnLSR read clears UnLSR[2].
Time of parity error detection is dependent on UnFCR[0].
Note: A parity error is associated with the character at the top
of the UARTn RBR FIFO.
0
Parity error status is inactive.
1 Parity error status is active.
3 Framing Error
(FE)
0
When the stop bit of a received character is a logic 0, a
framing error occurs. An UnLSR read clears UnLSR[3]. The
time of the framing error detection is dependent on UnFCR0.
Upon detection of a framing error, the Rx will attempt to
resynchronize to the data and assume that the bad stop bit is
actually an early start bit. However, it cannot be assumed that
the next received byte will be correct even if there is no
Framing Error.
Note: A framing error is associated with the character at the
top of the UARTn RBR FIFO.
0
Framing error status is inactive.
1 Framing error status is active.
4 Break
Interrupt
(BI)
0
When RXDn is held in the spacing state (all 0’s) for one full
character transmission (start, data, parity, stop), a break
interrupt occurs. Once the break condition has been detected,
the receiver goes idle until RXDn goes to marking state (all
1’s). An UnLSR read clears this status bit. The time of break
detection is dependent on UnFCR[0].
Note: The break interrupt is associated with the character at
the top of the UARTn RBR FIFO.
0
Break interrupt status is inactive.
1 Break interrupt status is active.
5 Transmitter
Holding
Register
Empty
(THRE))
0
THRE is set immediately upon detection of an empty UARTn
THR and is cleared on a UnTHR write. 1
UnTHR contains valid data.
1 UnTHR is empty.
6 Transmitter
Empty
(TEMT)
0
TEMT is set when both UnTHR and UnTSR are empty; TEMT
is cleared when either the UnTSR or the UnTHR contain valid
data. 1
UnTHR and/or the UnTSR contains valid data.
1 UnTHR and the UnTSR are empty.
7 Error in RX
FIFO
(RXFE)
0
UnLSR[7] is set when a character with a Rx error such as
framing error, parity error or break interrupt, is loaded into the
UnRBR. This bit is cleared when the UnLSR register is read
and there are no subsequent errors in the UARTn FIFO. 0
UnRBR contains no UARTn RX errors or UnFCR[0]=0.
1 UARTn RBR contains at least one UARTn RX error.
Table 387. UARTn Line Status Register (U0LSR - address 0xE000 C014,
U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only) bit description
Bit Symbol Value Description Reset
Value