Nxp semiconductors – NXP Semiconductors LPC24XX UM10237 User Manual
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UM10237_4
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 04 — 26 August 2009
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NXP Semiconductors
UM10237
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
4.2.9 Error conditions
An error during a DMA transfer is flagged directly by the peripheral by asserting an Error
response on the AHB bus during the transfer. The GPDMA automatically disables the
DMA stream after the current transfer has completed, and can optionally generate an
error interrupt to the CPU. This error interrupt can be masked.
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4/[7:0]
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78787878
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Table 650. Endian behavior
Source
Endian
Destination
Endian
Source
Width
Destination
Width
Source
Transfer no/
byte Lane
Source
Data
Destination
Transfer no/
byte Lane
Destination
Data