NXP Semiconductors LPC24XX UM10237 - Manual (Page 482)

UM10237_4 © NXP B.V. 2009. All rights reserved.
User manual Rev. 04 — 26 August 2009 482 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
8 IDI 0 (reset)
1 (set) ID Ready Interrupt -- this bit is set if the IDIE bit in
CANxIER is 1, and a CAN Identifier has been
received (a message was successfully transmitted or
aborted). This bit is set whenever a message was
successfully transmitted or aborted and the IDIE bit is
set in the IER reg. 0 0
9 TI2 0 (reset)
1 (set) Transmit Interrupt 2. This bit is set when the TBS2 bit
in CANxSR goes from 0 to 1 (whenever a message
out of TXB2 was successfully transmitted or aborted),
indicating that Transmit buffer 2 is available, and the
TIE2 bit in CANxIER is 1. 0 0
10 TI3 0 (reset)
1 (set) Transmit Interrupt 3. This bit is set when the TBS3 bit
in CANxSR goes from 0 to 1 (whenever a message
out of TXB3 was successfully transmitted or aborted),
indicating that Transmit buffer 3 is available, and the
TIE3 bit in CANxIER is 1. 0 0
15:11 - - Reserved, user software should not write ones to
reserved bits. 0 0
Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR -
address 0xE004 800C) bit description
Bit Symbol Value Function Reset
Value RM
Set