NXP Semiconductors LPC24XX UM10237 - Manual (Page 180)

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User manual Rev. 04 — 26 August 2009 180 of 792
NXP Semiconductors
UM10237
Chapter 9: LPC24XX Pin connect
5.2 Pin Function Select Register 1 (PINSEL1 - 0xE002 C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in
Table 9–131 . The direction control bit in the IO0DIR (or the FIO0DIR register if the
enhanced GPIO function is selected for port 0) register is effective only when the GPIO
function is selected for a pin. For other functions direction is controlled automatically.
7:6 P0[3] GPIO Port 0.3 RXD0 Reserved Reserved 00
9:8 P0[4] GPIO Port 0.4 I2SRX_CLK/
LCDVD[0] RD2 CAP2[0] 00
11:10 P0[5] GPIO Port 0.5 I2SRX_WS/
LCDVD[1] TD2 CAP2[1] 00
13:12 P0[6] GPIO Port 0.6 I2SRX_SDA/
LCDVD[8] SSEL1 MAT2[0] 00
15:14 P0[7] GPIO Port 0.7 I2STX_CLK/
LCDVD[9] SCK1 MAT2[1] 00
17:16 P0[8] GPIO Port 0.8 I2STX_WS/
LCDVD[16] MISO1 MAT2[2] 00
19:18 P0[9] GPIO Port 0.9 I2STX_SDA/
LCDVD[17] MOSI1 MAT2[3] 00
21:20 P0[10] GPIO Port 0.10 TXD2 SDA2 MAT3[0] 00
23:22 P0[11] GPIO Port 0.11 RXD2 SCL2 MAT3[1] 00
25:24 P0[12] GPIO Port 0.12 USB_PPWR2 MISO1 AD0[6] 00
27:26 P0[13] GPIO Port 0.13 USB_UP_LED2 MOSI1 AD0[7] 00
29:28 P0[14] GPIO Port 0.14 USB_HSTEN2 USB_CONN
ECT2 SSEL1 00
31:30 P0[15] GPIO Port 0.15 TXD1 SCK0 SCK 00
Table 130. Pin function select register 0 (PINSEL0 - address 0xE002 C000) bit description
PINSEL0 Pin
name
Function when
00 Function when 01 Function
when 10 Function
when 11 Reset
value
Table 131. Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description
PINSEL1 Pin
name
Function when
00 Function
when 01 Function
when 10 Function
when 11 Reset
value
1:0 P0[16] GPIO Port 0.16 RXD1 SSEL0 SSEL 00
3:2 P0[17] GPIO Port 0.17 CTS1 MISO0 MISO 00
5:4 P0[18] GPIO Port 0.18 DCD1 MOSI0 MOSI 00
7:6 P0[19] GPIO Port 0.19 DSR1 MCICLK SDA1 00
9:8 P0[20] GPIO Port 0.20 DTR1 MCICMD SCL1 00
11:10 P0[21] GPIO Port 0.21 RI1 MCIPWR RD1 00
13:12 P0[22] GPIO Port 0.22 RTS1 MCIDAT0 TD1 00
15:14 P0[23] GPIO Port 0.23 AD0[0] I2SRX_CLK CAP3[0] 00
17:16 P0[24] GPIO Port 0.24 AD0[1] I2SRX_WS CAP3[1] 00
19:18 P0[25] GPIO Port 0.25 AD0[2] I2SRX_SDA TXD3 00
21:20 P0[26] GPIO Port 0.26 AD0[3] AOUT RXD3 00
23:22 P0[27] [1] GPIO Port 0.27 SDA0 Reserved Reserved 00
25:24 P0[28] [1] GPIO Port 0.28 SCL0 Reserved Reserved 00