NXP Semiconductors LPC24XX UM10237 - Manual (Page 119)

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User manual Rev. 04 — 20 August 2009 119 of 792
NXP Semiconductors
UM10237
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
Fig 22. Block diagram of the Vectored Interrupt Controller
IntEnableClear
[31:0]
SoftIntClear
[31:0]
IntEnable
[31:0]
SoftInt
[31:0]
VICINT
SOURCE
[31:0]
IntSelect
[31:0]
RawIntr
[31:0]
FIQStatus
[31:0]
IRQStatus
[31:0]
FIQStatus
[31:0]
FIQ
interrupt request, masking, and selection
VectPriority0
[3:0]
PRIORITY
MASKING
LOGIC
VectAddr0
[31:0]
IRQStatus
[0]
SWPriorityMask [0]
HWPriorityMask [0]
VectIRQ0
Vect Addr0
[31:0]
D Q D Q
vectored interrupt 0
PRIORITY
LOGIC
VectAddr
[31:0]
status registers and FIQ generation
Vect
AddrOut
IRQStatus
[1]
VectIRQ1
Vect Addr1
[31:0]
vectored interrupt 1
IRQStatus
[31]
VectIRQ31
Vect Addr31
[31:0]
vectored interrupt 31
IRQ
vector select
for highest priority
interrupt
IRQStatus
[31:0]
SWPriorityMask
[31:0]
HWPriorityMask [31:0]
SWPriorityMask [31:0]
prioritization and vector generation