NXP Semiconductors LPC24XX UM10237 - Manual (Page 650)

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User manual Rev. 04 — 26 August 2009 650 of 792
NXP Semiconductors
UM10237
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
[1] Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset. These
registers must be initialized by software if the RTC is enabled. Reset Value reflects the data stored in used
bits only. It does not include reserved bits content.
6.1 RTC interrupts
Interrupt generation is controlled through the Interrupt Location Register (ILR), Counter
Increment Interrupt Register (CIIR), the alarm registers, and the Alarm Mask Register
(AMR). Interrupts are generated only by the transition into the interrupt state. The ILR
separately enables CIIR and AMR interrupts. Each bit in CIIR corresponds to one of the
time counters. If CIIR is enabled for a particular counter, then every time the counter is
incremented an interrupt is generated. The alarm registers allow the user to specify a date
and time for an interrupt to be generated. The AMR provides a mechanism to mask alarm
compares. If all nonmasked alarm registers match the value in their corresponding time
counter, then an interrupt is generated.
The RTC interrupt can bring the microcontroller out of Power-down and Deep power-down
mode if the RTC is operating from its own oscillator on the RTCX1-2 pins. When the RTC
interrupt is enabled for wakeup and its selected event occurs, the oscillator wakeup cycle
associated with the XTAL1/2 pins is started. For details on the RTC based wakeup
process see
Section 4–3.4.8 “Interrupt Wakeup Register (INTWAKE - 0xE01F C144)” on
page 63 and Section 4–5 “Wakeup timer” on page 67 .
6.2 Miscellaneous register group
6.2.1 Interrupt Location Register (ILR - 0xE002 4000)
The Interrupt Location Register specifies which blocks are generating an interrupt (see
Table 26–567 ). Writing a one to the appropriate bit clears the corresponding interrupt.
Writing a zero has no effect. This allows the programmer to read this register and write
back the same value to clear only the interrupt that is detected by the read.
ALYEAR Alarm value for Year R/W NC 0xE002 407C
PREINT Prescaler value, integer portion R/W 0 0xE002 4080
PREFRAC Prescaler value, fractional portion R/W 0 0xE002 4084
Table 566. Summary of Real-Time Clock registers …continued
Name Description Access Reset
Value
[1]
Address
Table 567. Interrupt Location Register (ILR - address 0xE002 4000) bit description
Bit Symbol Description Reset
value
0 RTCCIF When one, the Counter Increment Interrupt block generated an interrupt.
Writing a one to this bit location clears the counter increment interrupt. NC
1 RTCALF When one, the alarm registers generated an interrupt. Writing a one to
this bit location clears the alarm interrupt. NC
2 RTSSF When one, the Counter Increment Sub-Seconds interrupt is generated.
The interrupt rate is determined by the CISS register. NC
7:2 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA