NXP Semiconductors LPC24XX UM10237 - Manual (Page 588)

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User manual Rev. 04 — 26 August 2009 588 of 792
NXP Semiconductors
UM10237
Chapter 22: LPC24XX I 2 C interfaces I 2 C0/1/2
9.2 Master Receiver mode
In the master receiver mode, a number of data bytes are received from a slave transmitter
(see
Figure 22–121 ). The transfer is initialized as in the master transmitter mode. When
the start condition has been transmitted, the interrupt service routine must load I2DAT with
the 7 bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then
be cleared before the serial transfer can continue.
When the slave address and the data direction bit have been transmitted and an
acknowledgment bit has been received, the serial interrupt flag (SI) is set again, and a
number of status codes in I2STAT are possible. These are 0x40, 0x48, or 0x38 for the
master mode and also 0x68, 0x78, or 0xB0 if the slave mode was enabled (AA = 1). The
appropriate action to be taken for each of these status codes is detailed in
Table 22–526 .
After a repeated start condition (state 0x10), the I 2 C block may switch to the master
transmitter mode by loading I2DAT with SLA+W.
9.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see
Figure 22–122 ). To initiate the slave receiver mode, I2ADR and I2CON must be
loaded as follows:
The upper 7 bits are the address to which the I 2 C block will respond when addressed by a
master. If the LSB (GC) is set, the I 2 C block will respond to the general call address
(0x00); otherwise it ignores the general call address.
The I 2 C bus rate settings do not affect the I 2 C block in the slave mode. I2EN must be set
to logic 1 to enable the I 2 C block. The AA bit must be set to enable the I 2 C block to
acknowledge its own slave address or the general call address. STA, STO, and SI must
be reset.
When I2ADR and I2CON have been initialized, the I 2 C block waits until it is addressed by
its own slave address followed by the data direction bit which must be “0” (W) for the I 2 C
block to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag (SI) is set and a valid status code can be read
from I2STAT. This status code is used to vector to a state service routine. The appropriate
action to be taken for each of these status codes is detailed in
Table 22–527 . The slave
receiver mode may also be entered if arbitration is lost while the I 2 C block is in the master
mode (see status 0x68 and 0x78).
Table 523. I2C0ADR and I2C1ADR usage in Slave Receiver mode
Bit 7 6 5 4 3 2 1 0
Symbol own slave 7 bit address GC
Table 524. I2C0CONSET and I2C1CONSET used to initialize Slave Receiver mode
Bit 7 6 5 4 3 2 1 0
Symbol - I2EN STA STO SI AA - -
Value - 1 0 0 0 1 - -