NXP Semiconductors LPC24XX UM10237 - Manual (Page 478)

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User manual Rev. 04 — 26 August 2009 478 of 792
NXP Semiconductors
UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
[2] If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the
bits. The requested transmission may only be cancelled by setting the Abort Transmission bit.
[3] The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a
more urgent message before. A transmission already in progress is not stopped. In order to see if the original message has been either
transmitted successfully or aborted, the Transmission Complete Status bit should be checked. This should be done after the Transmit
Buffer Status bit has been set to '1' or a Transmit Interrupt has been generated.
[4] After reading the contents of the Receive Buffer, the CPU can release this memory space by setting the Release Receive Buffer bit '1'.
This may result in another message becoming immediately available. If there is no other message available, the Receive Interrupt bit is
reset. If the RRB command is given, it will take at least 2 internal clock cycles before a new interrupt is generated.
[5] This command bit is used to clear the Data Overrun condition signalled by the Data Overrun Status bit. As long as the Data Overrun
Status bit is set no further Data Overrun Interrupt is generated.
[6] Upon Self Reception Request, a message is transmitted and simultaneously received if the Acceptance Filter is set to the corresponding
identifier. A receive and a transmit interrupt will indicate correct self reception (see also Self Test Mode in
Section 18–8.1 “Mode
Register (CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000)” ).
8.3 Global Status Register (CAN1GSR - 0xE004 x008, CAN2GSR -
0xE004 8008)
The content of the Global Status Register reflects the status of the CAN Controller. This
register is read-only, except that the Error Counters can be written when the RM bit in the
CANMOD register is 1. Bits not listed read as 0 and should be written as 0.
Table 422. Global Status Register (CAN1GSR - address 0xE004 4008, CAN2GSR - address 0xE004 8008) bit
description
Bit Symbol Value Function Reset
Value RM
Set
0 RBS [1] Receive Buffer Status. 0 0
0 (empty) No message is available.
1 (full) At least one complete message is received by the Double Receive Buffer
and available in the CANxRFS, CANxRID, and if applicable the CANxRDA
and CANxRDB registers. This bit is cleared by the Release Receive Buffer
command in CANxCMR, if no subsequent received message is available.
1 DOS [2] Data Overrun Status. 0 0
0 (absent) No data overrun has occurred since the last Clear Data Overrun command
was given/written to CANxCMR (or since Reset).
1 (overrun) A message was lost because the preceding message to this CAN controller
was not read and released quickly enough (there was not enough space for
a new message in the Double Receive Buffer).
2 TBS Transmit Buffer Status. 1 1
0 (locked) At least one of the Transmit Buffers is not available for the CPU, i.e. at least
one previously queued message for this CAN controller has not yet been
sent, and therefore software should not write to the CANxTFI, CANxTID,
CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).
1 (released) All three Transmit Buffers are available for the CPU. No transmit message is
pending for this CAN controller (in any of the 3 Tx buffers), and software may
write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
3 TCS [3] Transmit Complete Status. 1 x
0 (incomplete) At least one requested transmission has not been successfully completed
yet.
1 (complete) All requested transmission(s) has (have) been successfully completed.