NXP Semiconductors LPC24XX UM10237 - Manual (Page 197)

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User manual Rev. 04 — 26 August 2009 197 of 792
NXP Semiconductors
UM10237
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 158. Summary of GPIO registers (legacy APB accessible registers)
Generic
Name Description Access Reset
value [1]
PORTn Register
Address & Name
IOPIN GPIO Port Pin value register. The current state of the GPIO
configured port pins can always be read from this register,
regardless of pin direction. By writing to this register port’s pins will
be set to the desired level instantaneously. R/W NA IO0PIN - 0xE002 8000
IO1PIN - 0xE002 8010
IOSET GPIO Port Output Set register. This register controls the state of
output pins in conjunction with the IOCLR register. Writing ones
produces highs at the corresponding port pins. Writing zeroes has
no effect. R/W 0x0 IO0SET - 0xE002 8004
IO1SET - 0xE002 8014
IODIR GPIO Port Direction control register. This register individually
controls the direction of each port pin. R/W 0x0 IO0DIR - 0xE002 8008
IO1DIR - 0xE002 8018
IOCLR GPIO Port Output Clear register. This register controls the state of
output pins. Writing ones produces lows at the corresponding port
pins and clears the corresponding bits in the IOSET register.
Writing zeroes has no effect. WO 0x0 IO0CLR - 0xE002 800C
IO1CLR - 0xE002 801C