NXP Semiconductors LPC24XX UM10237 - Manual (Page 419)

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User manual Rev. 04 — 26 August 2009 419 of 792
NXP Semiconductors
UM10237
Chapter 15: LPC24XX USB OTG controller
Load and enable OTG timer
/* The following assumes that the OTG timer has previously been */
/* configured for a time scale of 1 ms (TMR_SCALE = “10”) */
/* and monoshot mode (TMR_MODE = 0) */
/* Load the timeout value to implement the a_aidl_bdis_tmr timer */
/* the minimum value is 200 ms */
OTG_TIMER = 200;
/* Enable the timer */
OTG_STAT_CTRL |= TMR_EN;
Stop OTG timer
/* Disable the timer – causes TMR_CNT to be reset to 0 */
OTG_STAT_CTRL &= ~TMR_EN;
/* Clear TMR interrupt */
OTG_INT_CLR = TMR;
Suspend host on port 1
/* Write to PortSuspendStatus bit to suspend host port 1 – */
/* this example demonstrates the low-level action software needs to take. */
/* The host stack code where this is done will be somewhat more involved. */
HC_RH_PORT_STAT1 = PSS;
9. Clocking and power management
The OTG controller clocking is shown in Figure 15–64 .
A clock switch controls each clock with the exception of ahb_slave_clk. When the enable
of the clock switch is asserted, its clock output is turned on and its CLK_ON output is
asserted. The CLK_ON signals are observable in the OTGClkSt register.
To conserve power, the clocks to the Device, Host, OTG, and I2C controllers can be
disabled when not in use by clearing the respective CLK_EN bit in the OTGClkCtrl
register. When the entire USB block is not in use, all of its clocks can be disabled by
clearing the PCUSB bit in the PCONP register.
When software wishes to access registers in one of the controllers, it should first ensure
that the respective controller’s 48 MHz clock is enabled by setting its CLK_EN bit in the
OTGClkCtrl register and then poll the corresponding CLK_ON bit in OTGClkSt until set.
Once set, the controller’s clock will remain enabled until CLK_EN is cleared by software.
Accessing the register of a controller when its 48 MHz clock is not enabled will result in a
data abort exception.