Texas Instruments MSP430x1xx - Manual (Page 114)

Basic Clock Module Operating Modes
7-14
7.4 Basic Clock Module Operating Modes
Control bits SCG0, SCG1, OscOff, and CPUOff in the status register configure
the operating mode, as discussed in Chapter 3,
System Resets, Interrupts and
Operating Modes.
The digitally-controlled oscillator is disabled when not used for MCLK or
SMCLK. The dc generator must be switched off separately, but is switched on
automatically when the DCOCLK signal is used, either for MCLK or SMCLK.
7.4.1 Starting From Power Up Clear (PUC)
On a valid PUC, the internal resistor is selected for the dc generator, R
sel
= 4,
and DCO = 3, allowing the oscillator to operate at a medium frequency and
independently from external conditions. ACLK is sourced from LFXT1 in the
LF mode and configured to operate with a watch crystal; MCLK and SMCLK
are sourced from DCOCLK. Because the CPU executes code from MCLK,
which is sourced from the fast-starting DCO, code execution from PUC is fast,
typically less than 6
µ
s. After a PUC, user software selects the best basic clock
configuration for the application.
7.4.2 Adjusting the Basic Clock
The control registers of the Basic Clock are under full software control. If clock
requirements other than those of the default from PUC are necessary, the Ba-
sic Clock can be configured or reconfigured by software at any time during pro-
gram execution.
- ACLKGEN from LFXT1 crystal, resonator, or external-clock source and
divided by 1, 2, 4, or 8. If no LFXTCLK clock signal is needed in the
application, the OscOff bit should be set in the status register.
- SCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only)
and divided by 1, 2, 4, or 8. The SCG1 bit in the status register enables
or disables SMCLK.
- MCLKGEN from LFXTCLK, DCOCLK, or XT2CLK (x13x and x14x only)
and divided by 1, 2, 4, or 8. When set, the CPUOff bit in the status register
enables or disables MCLK.
- DCOCLK frequency is adjusted using the RSEL, DCO, and MOD bits. The
DCOCLK clock source is stopped when not used, and the dc generator
can be disabled by the SCG0 bit in the status register (when set).
- The XT2 oscillator sources XT2CLK (x13x and x14x only) by clearing the
XT2Off bit.
User software can modify the Basic Clock to meet the system requirements
at any time using the full MSP430 instruction set. A few examples follow:
bis.b #007h,&BCSCTL1 ; RSEL=7
mov.b #081h,&BCSCTL1 ; XT2off, RSEL=1
bis.b #070h,&BCSCTL1 ; ACLK= high-speed XTAL/8
bis.b #008h,&BCSCTL2 ; SMCLK=LFXT1
inc.b &DCOCTL ; Increase DCOCLK
dec.b &DCOCTL ; Decrease DCOCLK