Texas Instruments MSP430x1xx - Manual (Page 41)

Interrupt Processing
3-11
System Resets, Interrupts, and Operating Modes
Figure 3–9. Status Register (SR)
SCG0 GIE Z C
rw-0
15 0
Reserved For Future Enhancements N
CPU
Off
OSC
Off
SCG1 V
8 7
Apart from the GIE bit, other sources of interrupt requests can be enabled/
disabled individually or in groups. The interrupt enable flags are located
together within two addresses of the special-function registers (SFRs). The
program-flow conditions on interrupt requests can be easily adjusted using the
interrupt enable masks. The hardware serves the highest priority within the
empowered interrupt source.
3.4.1 Interrupt Control Bits in Special-Function Registers (SFRs)
Most of the interrupt control bits, interrupt flags, and interrupt enable bits are
collected in SFRs under a few addresses, as shown in Table 3–1. The SFRs
are located in the lower address range and are implemented in byte format.
SFRs must be accessed using byte instructions.
Table 3–1. Interrupt Control Bits in SFRs
Address 7 0
000Fh Not yet defined or implemented
000Eh Not yet defined or implemented
000Dh Not yet defined or implemented
000Ch Not yet defined or implemented
000Bh Not yet defined or implemented
000Ah Not yet defined or implemented
0009h Not yet defined or implemented
0008h Not yet defined or implemented
0007h Not yet defined or implemented
0006h Not yet defined or implemented
0005h Module enable 2 (ME2.x)
0004h Module enable 1 (ME1.x)
0003h Interrupt flag reg. 2 (IFG2.x)
0002h Interrupt flag reg. 1 (IFG1.x)
0001h Interrupt enable 2 (IE2.x)
0000h Interrupt enable 1 (IE1.x)
The MSP430 family supports SFRs by applying the correct logic and functions
to each individual module. Each module interrupt source can be individually
enabled or disable using the bits described in Table 3–2.
The interrupt-flag registers are described in Table 3–3. The module-enable
bits are described in Table 3–4.