Texas Instruments MSP430x1xx - Manual (Page 313)

Sampling
15-23
ADC12
Figure 15–15. Sample and Conversion, Basic Signal Timing
SAMPCON
Sample
Conversion
and Hold
Start
Sampling
Stop Sampling
Start Conversion
Stop Conversion
The analog input signal must be valid and steady during the sampling period
in order to obtain an accurate conversion. It is also desirable not to have any
digital activity on any adjacent channels during the whole conversion period
to ensure that errors due to supply glitching, ground bounce, or crosstalk do
not corrupt the conversion results.
In addition, gains and losses in internal charge limit the hold time. The user
should ensure that the data sheet limits are not violated. Otherwise, the
sampled analog voltage may increase or decrease, resulting in false conver-
sion values.
15.7.2 Sample Signal Input Selection
The SAMPCON signal, which controls sample timing and the start of a
conversion, may be sourced by one of several signals. SAMPCON may be
sourced directly from one of the signals available at the input selection switch
(see Figure 15–16), further called sample-signal input, or from the integrated
sampling timer. When the sampling timer is used to source SAMPCON, the
sample-signal input is used to trigger the sampling timer.
The sample-signal input is selected by the SHS bits in ADC12CTL1. There are
four choices for the sample-signal input: ADC12SC, Timer_A.OUT1,
Timer_B.OUT0, and Timer_B.OUT1. The polarity of the sample-signal input
may be selected by the ISSH bit (see Figure 15–16). Also, the sample-signal
input is passed to the sampling timer or to the SAMPCON signal under control
of the ENC bit. This is discussed in detail further ahead.
ADC12SC is a control bit located in ADC12CTL0. Its value is set by software.
Depending on the selected sampling mode, this bit allows the software to
either start a sample-and-conversion (S/C) cycle (SHP=1), or to completely
control the sampling period (SHP=0).
The sample-signal input can be asynchronous to a conversion-enable, and is
synchronized and enabled by the ENC bit. Without synchronization, the first
sampling period after the ENC bit is set could be erroneous, depending on
where the ENC bit is set within the cycle of the input signal. In Figure 15–18,
for example, note that the ENC bit is set in the middle of a high pulse from the
sample-signal input. If the sample-input signal were simply passed directly to
the S/H, the first conversion of the example would be erroneous because the
first sampling period is too short.