Texas Instruments MSP430x1xx - Manual (Page 70)

CPU Registers
5-6
The RISC instruction set of the MSP430 only has 27 instructions. However, the
constant generator allows the MSP430 assembler to support 24 additional,
emulated instructions. For example, the single-operand instruction:
CLR dst
is emulated by the double-operand instruction with the same length:
MOV R3,dst
or the equivalent
MOV
#0,dst
where #0 is replaced by the assembler, and R3 is used with As = 00, which
results in:
- One word instruction
- No additional control operation or hardware within the CPU
- Register-addressing mode for source: no additional fetch cycle for the
constant (#0)