Texas Instruments MSP430x1xx - Manual (Page 330)

ADC12 Control Registers
15-40
RETI ; Back to main program 5
;
ADC12MOD1 ; Vector 8: ADC12MEM1 was loaded
; (ADC12IFG.1)
ADD &ADC12MEM1,R6 ; ADC12IFG1 is reset due to access
; of ADC memory
... ; Task starts here
RETI ; Back to main program 5
; The Module 3 handler shows a way to look if any other
;interrupt is pending: 5 cycles have to be spent, but 9 cycles
; may be saved if another interrupt is pending
;
ADC12MOD0 ; Vector 6: ADC12MEM0 was loaded
; (ADC12IFG.0)
... ; First instruction to be executed x
... ; Task starts here
JMP ADC12_HND ; With this instruction the software
; does not leave the handler; it looks
; for pending ADC12 interrupts 2
;
.SECT ”VECTORS”,0FFF4h ; Interrupt Vectors
.WORD ADC12_HND ; Vector for 12-bit ADC interrupt
; flags and overflow
Note: Basic Clock System
If the CPU clock MCLK is turned off (CPUOff=1), then two or three additional
cycles need to be added for synchronous start of the CPU system. The delta
of one clock cycle is caused when clocks are asynchronous to the restart of
CPU clock MCLK.