Texas Instruments MSP430x1xx - Manual (Page 69)

CPU Registers
5-5
16-Bit CPU
Note: Status Register Bits V, N, Z, and C
The status register bits V, N, Z, and C are modified only with the appropriate
instruction. For additional information, see the detailed description of the
instruction set in Appendix B.
5.1.4 The Constant Generator Registers CG1 and CG2
Commonly-used constants are generated with the constant generator
registers R2 and R3, without requiring an additional 16-bit word of program
code. The constant used for immediate values is defined by the addressing
mode bits (As) as described in Table 5–3. See Section 5.3 for a description of
the addressing mode bits (As).
Table 5–3. Values of Constant Generators CG1, CG2
Register As Constant Remarks
R2 00 – – – – – Register mode
R2 01 (0) Absolute address mode
R2 10 00004h +4, bit processing
R2 11 00008h +8, bit processing
R3 00 00000h 0, word processing
R3 01 00001h +1
R3 10 00002h +2, bit processing
R3 11 0FFFFh –1, word processing
The major advantages of this type of constant generation are:
- No special instructions required
- Reduced code memory requirements: no additional word for the six most
used constants
- Reduced instruction cycle time: no code memory access to retrieve the
constant
The assembler uses the constant generator automatically if one of the six
constants is used as a source operand in the immediate addressing mode.
The status register SR/R2, used as a source or destination register, can be
used in the register mode only. The remaining combinations of
addressing-mode bits are used to support absolute-address modes and bit
processing without any additional code. Registers R2 and R3, used in the
constant mode, cannot be addressed explicitly; they act like source-only
registers.