Texas Instruments MSP430x1xx - Manual (Page 379)

Instruction Set Overview
B-29 Instruction Set Description
* EINT Enable (general) interrupts
Syntax EINT
Operation 1
→
GIE
or
(0008h .OR. SR –> SR / .NOT.src .OR. dst –> dst)
Emulation BIS #8,SR
Description All interrupts are enabled.
The constant #08h and the status register SR are logically ORed. The result
is placed into the SR.
Status Bits N: Not affected
Z: Not affected
C: Not affected
V: Not affected
Mode Bits GIE is set. OscOff and CPUOff are not affected.
Example The general interrupt enable (GIE) bit in the status register is set.
; Interrupt routine of port P0.2 to P0.7
; The interrupt level is the lowest in the system
; P0IN is the address of the register where all port bits are read. P0IFG is the address of
; the register where all interrupt events are latched.
;
PUSH.B &P0IN
BIC.B @SP,&P0IFG ; Reset only accepted flags
EINT ; Preset port 0 interrupt flags stored on stack
; other interrupts are allowed
BIT #Mask,@SP
JEQ MaskOK ; Flags are present identically to mask: jump
......
MaskOK BIC #Mask,@SP
......
INCD
SP ; Housekeeping: inverse to PUSH instruction
; at the start of interrupt subroutine. Corrects
; the stack pointer.
RETI
Note: Enable Interrupt
The instruction following the enable interrupt instruction (EINT) is always
executed, even if an interrupt service request is pending when the interrupts
are enable.