Texas Instruments MSP430x1xx - Manual (Page 234)

Control and Status Registers
12-18
Bit 3: The receive-start edge-control bit, if set, requests a receive
interrupt service. For a successful interrupt service, the
corresponding enable bits URXIE and GIE must be set. The
advantage of this bit is that it starts the controller clock system,
including MCLK, along with the interrupt service, and keeps it
running by modifying the mode control bits.
Bits 4, 5: Source select 0 and 1
The source select bit defines which clock source is used for
baud-rate generation:
SSEL1, SSEL0
0 External clock, UCLKI
1 ACLK
2, 3 SMCLK
Bit 6: Clock polarity CKPL
The CKPL bit controls the polarity of the UCLKI signal.
CKPL = 0: The UCLKI signal has the same polarity as the
UCLK signal.
CKPL = 1: The UCLKI signal has an inverted polarity to the
UCLK signal.
Bit 7: Unused
12.5.3 Receiver Control Register URCTL
The receiver-control register (URCTL), shown in Figure 12–18, controls the
USART hardware associated with the receiver operation and holds error and
wake-up conditions modified by the latest character written to the receive
buffer (URXBUF). Once any one of the bits FE, PE, OE, BRK, RXERR, or
RXWake is set, none are reset by receiving another character. The bits are
reset by accessing the receive buffer, by a USART software reset (SWRST),
by a system reset PUC signal, or by an instruction.
Figure 12–18. Receiver-Control Register URCTL
7 0
OE PE BRK RXERR URXEIE
rw–0
FE RXWake URXWIE
rw–0 rw–0 rw–0 rw–0 rw–0 rw–0 rw–0
URCTL0, 072h
URCTL1, 07Ah
Bit 0: The receive error bit (RXERR) indicates that one or more error
flags (FE, PE, OE, or BRK) is set. It is not reset when the error
flags are cleared by instruction.
Bit 1: Receiver wake-up detect
The RXWake bit is set when a received character is an address
character and is transferred into the receive buffer.
Address-bit multiprocessor mode: RXWake is set when the
address bit is set in the
character received.
Idle-line multiprocessor mode: RXWake is set if an idle
URXD line is detected
(11 bits of mark level) in
front of the received
character.