Texas Instruments MSP430x1xx - Manual (Page 36)

MSP430 Interrupt-Priority Scheme
3-6
3.3 MSP430 Interrupt-Priority Scheme
The interrupt priority of the modules, as shown in Figure 3–4, is defined by the
arrangement of the modules in the connection chain: the nearer a module is
to the CPU/NMIRS, the higher the priority.
Figure 3–4. Interrupt Priority Scheme
Bus
Grant
Module
1
Module
2
WD
Timer
Module
m
Module
n
1 2 1 2 1 2 1 2 1
NMIRS
GIE
CPU
OSCfault
Reset/NMI
PUC
Circuit
PUC
WDT Security Key
Priority
High
Low
MAB – 5LSBs
GMIRS
Flash Security Key
Flash ACCV
Reset and NMI, as shown in Figure 3–5, can only be used as alternative
interrupts because they use the same input pin. The associated control bits are
located in the watchdog timer control register shown in Figure 3–6, and are
password protected.