Texas Instruments MSP430x1xx User Manual

Page 357

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Instruction Set Overview

B-7

Instruction Set Description

The following list describes the emulated instruction short form.

Mnemonic

Description

Status Bits

Emulation

V N Z C

Arithmetical instructions
ADC[.W]

dst

Add carry to destination

*

*

*

*

ADDC

#0,dst

ADC.B

dst

Add carry to destination

*

*

*

*

ADDC.B

#0,dst

DADC[.W]

dst

Add carry decimal to destination

*

*

*

*

DADD

#0,dst

DADC.B

dst

Add carry decimal to destination

*

*

*

*

DADD.B

#0,dst

DEC[.W]

dst

Decrement destination

*

*

*

*

SUB

#1,dst

DEC.B

dst

Decrement destination

*

*

*

*

SUB.B

#1,dst

DECD[.W]

dst

Double-decrement destination

*

*

*

*

SUB

#2,dst

DECD.B

dst

Double-decrement destination

*

*

*

*

SUB.B

#2,dst

INC[.W]

dst

Increment destination

*

*

*

*

ADD

#1,dst

INC.B

dst

Increment destination

*

*

*

*

ADD.B

#1,dst

INCD[.W]

dst

Increment destination

*

*

*

*

ADD

#2,dst

INCD.B

dst

Increment destination

*

*

*

*

ADD.B

#2,dst

SBC[.W]

dst

Subtract carry from destination

*

*

*

*

SUBC

#0,dst

SBC.B

dst

Subtract carry from destination

*

*

*

*

SUBC.B

#0,dst

Logical instructions
INV[.W]

dst

Invert destination

*

*

*

*

XOR

#0FFFFh,dst

INV.B

dst

Invert destination

*

*

*

*

XOR.B

#0FFFFh,dst

RLA[.W]

dst

Rotate left arithmetically

*

*

*

*

ADD

dst,dst

RLA.B

dst

Rotate left arithmetically

*

*

*

*

ADD.B

dst,dst

RLC[.W]

dst

Rotate left through carry

*

*

*

*

ADDC

dst,dst

RLC.B

dst

Rotate left through carry

*

*

*

*

ADDC.B

dst,dst

Data instructions (common use)
CLR[.W]

Clear destination

– –

– –

MOV

#0,dst

CLR.B

Clear destination

– –

– –

MOV.B

#0,dst

CLRC

Clear carry bit

– –

– 0

BIC

#1,SR

CLRN

Clear negative bit

– 0

– –

BIC

#4,SR

CLRZ

Clear zero bit

– –

0 –

BIC

#2,SR

POP

dst

Item from stack

– –

– –

MOV

@SP+,dst

SETC

Set carry bit

– –

– 1

BIS

#1,SR

SETN

Set negative bit

– 1

– –

BIS

#4,SR

SETZ

Set zero bit

– –

1 –

BIS

#2,SR

TST[.W]

dst

Test destination

0 *

*

1

CMP

#0,dst

TST.B

dst

Test destination

0 *

*

1

CMP.B

#0,dst

Program flow instructions
BR

dst

Branch to .......

– –

– –

MOV

dst,PC

DINT

Disable interrupt

– –

– –

BIC

#8,SR

EINT

Enable interrupt

– –

– –

BIS

#8,SR

NOP

No operation

– –

– –

MOV

#0h,#0h

RET

Return from subroutine

– –

– –

MOV

@SP+,PC

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