Texas Instruments MSP430x1xx - Manual (Page 314)

Sampling
15-24
To prevent this problem, synchronization logic is implemented in the sample
input selection switch. This ensures that the first sample-and-conversion cycle
begins with the first rising edge of the sample-input signal applied
after the
ENC bit is set. Additionally, the last sample-and-conversion begins with the
first rising edge of the sample-input signal
after ENC has been reset.
Figure 15–16. Synchronized Sample and Conversion Signal With Enable Conversion
Enable Conversion
ENC
Sample-Signal
SHI
Sample and conversions
Trigger signal enabled
tssync
tENC
esync
t
Input
15.7.3 Sampling Modes
The sampling circuitry has two modes of operation: pulse-sampling mode and
extended-sampling mode. In pulse-sampling mode, the sample-signal input
(selected by the SHS bits in ADC12CTL1) is used to trigger the internal sam-
pling timer, and the actual sample timing signal (SAMPCON) is then generated
by the sampling timer and is an integer multiple of the ADC12CLK signal.
In extended-sampling mode, the sampling-signal input bypasses the sample
timer and is used to source SAMPCON directly, therefore completely control-
ling the sample timing—asynchronously to ADC12CLK. Note that 13
ADC12CLK cycles are still required to complete one conversion.
15.7.3.1 Pulse-Sample Mode
In the pulse-sample mode, the sample-input signal, selected by the SHS bits,
triggers the sampling timer with its rising edge. The sampling timer then gener-
ates the sample timing. The sampling time is programmable by the SHT0 or
SHT1 bits located in ADC12CTL0. When conversion-memory registers
ADC12MEM0 to ADC12MEM7 are selected to store the conversion result(s),
the SHT0 bits are used to program the sampling time. When conversion-
memory registers ADC12MEM8 to ADC12MEM15 are selected for the con-
version data, the SHT1 bits are used to program the sampling timing. There-
fore, it is possible to program two different sampling times for a sequence of
conversions by using both upper and lower conversion-memory registers in
the sequence. This feature is useful when different external-source imped-
ance conditions exist and require different sample timings.