Figure 11–1. timer_b block diagram, Introduction 11-4 – Texas Instruments MSP430x1xx User Manual
Page 180
Introduction
11-4
Figure 11–1. Timer_B Block Diagram
Input
Divider
CLK1
16-Bit Timer
TPSSEL0
TPSSEL1
TBCLK
ACLK
SMCLK
0
1
2
3
RC
INCLK
ID1 ID0
15
0
Data
Timer Clock
POR/CLR
Mode
Control
MC1
MC0
Equ0
Carry/Zero
Set_TBIFG
16-Bit Timer
Capture
Mode
CCIS00
CCIS01
CCI0A
CCI0B
GND
0
1
2
3
VCC
CCI0
CCM00
CCM01
Capture/Compare
Register CCR0
15
0
TBCL0
Compare Latch
15
0
Output Unit 0
OM02
OM00
OM01
Out 0
Capture
EQU0
Capture/Compare Register CCR0
Timer Bus
Capture
Mode
CCIS10
CCIS11
CCI1A
CCI1B
GND
0
1
2
3
VCC
CCI1
CCM10
CCM11
Capture/Compare
Register CCR1
15
0
TBCL1
Comparator Latch
15
0
Output Unit 1
OM12
OM10
OM11
Out 1
Capture
EQU0
Capture/Compare Register CCR1
Capture
Mode
CCIS60
CCIS61
CCI6A
CCI6B
GND
0
1
2
3
VCC
CCI6
CCM60
CCM61
Capture/Compare
Register CCR6
15
0
15
0
Output Unit 6
OM62
OM60
OM61
Out 6
Capture
EQU0
Capture/Compare Register CCR6
Comparator 0
EQU0
Comparator 1
EQU1
Comparator 6
EQU6
Module 2
Module 3
Module 4
Module 5
8, 10, 12. or 16-Bit
TBCL6
Compare Latch