3 synchronization error – Texas Instruments MSP430x1xx User Manual

Page 244

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Baud Rate Considerations

12-28

Table 12–6.Commonly Used Baud Rates, Baud Rate Data, and Errors

Divide by

ACLK (32,768 Hz)

MCLK (1,048,576 Hz)

Baud

Rate

ACLK

MCLK

UBR1

UBR0

UMOD

Max.

TX

Error %

Max.

RX

Error %

Synchr.

RX

Error %

UBR1

UBR0

UMOD

Max. TX

Error%

Max. RX

Error %

75

436.91

13,981

1

B4

FF

–0.1/0.3

–0.1/0.3

±

2

36

9D

FF

0/0.1

±

2

110

297.89

9532.51

1

29

FF

0/0.5

0/0.5

±

3

25

3C

FF

0/0.1

±

3

150

218.45

6990.5

0

DA

55

0/0.4

0/0.4

±

2

1B

4E

FF

0/0.1

±

2

300

109.23

3495.25

0

6D

22

–0.3/0.7

–0.3/0.7

±

2

0D

A7

00

–0.1/0

±

2

600

54.61

1747.63

0

36

D5

– 1/1

– 1/1

±

2

06

D3

FF

0/0.3

±

2

1200

27.31

873.81

0

1B

03

– 4/3

– 4/3

±

2

03

69

FF

0/0.3

±

2

2400

13.65

436.91

0

0D

6B

6/3

– 6/3

±

4

01

B4

FF

0/0.3

±

2

4800

6.83

218.45

0

06

6F

– 9/11

– 9/11

±

7

0

DA

55

0/0.4

±

2

9600

3.41

109.23

0

03

4A

– 21/12

– 21/12

±

15

0

6D

03

–0.4/1

±

2

19,200

54.61

0

36

6B

–0.2/2

±

2

38,400

27.31

0

1B

03

– 4/3

±

2

76,800

13.65

0

0D

6B

– 6/3

±

4

115,200

9.10

0

09

08

– 5/7

±

7

The maximum error is calculated for the receive and transmit modes. The
receive-mode error is the accumulated time versus the ideal scanning time in
the middle of each bit. The transmit error is the accumulated timing error
versus the ideal time of the bit period.

The MSP430 USART peripheral interface allows baud rates nearly as high as
the clock rate. It has a low error accumulation as a result of modulating the
individual bit timing. In practice, an error margin of 20% to 30% supports
standard serial communication.

12.7.3 Synchronization Error

The synchronization error, shown in Figure 12–29, results from the
asynchronous timing between the URXD pin data signal and the internal clock
system. The receive signal is synchronized with the BRSCLK clock. The
BRSCLK clock is sixteen to thirty-one times faster than the bit timing, as
described.

BRSCLK = BRCLK

for

N

1F

BRSCLK = BRCLK/2

for

20h

N

3Fh

BRSCLK = BRCLK/4

for

40h

N

7Fh

BRSCLK = BRCLK/8

for

80h

N

FFh

BRSCLK = BRCLK/16

for

100

N

1FF

BRSCLK = BRCLK/32

for

200

N

3FFh

BRSCLK = BRCLK/64

for

400

N

7FFh

BRSCLK = BRCLK/128

for

800h

N

FFFh

BRSCLK = BRCLK/256

for

1000h

N

1FFFh

BRSCLK = BRCLK/512

for

2000h

N

3FFFh

BRSCLK = BRCLK/1024

for

4000h

N

7FFFh

BRSCLK = BRCLK/2048

for

8000h

N

FFFFh

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