Texas Instruments MSP430x1xx - Manual (Page 97)

Hardware Multiplier Registers
6-9
Hardware Multiplier
6.3 Hardware Multiplier Registers
Hardware multiplier registers are word structured, but can be accessed using
word or byte processing instructions. Table 6–2 describes the hardware
multiplier registers.
Table 6–2. Hardware Multiplier Registers
Register Short Form Register Type Address Initial State
Multiply Unsigned (Operand1) MPY Read/write 0130h Unchanged
Multiply Signed (Operand1) MPYS Read/write 0132h Unchanged
Multiply+Accumulate (Operand1) MAC Read/write 0134h Unchanged
Multiply Signed+Accumulate (Operand1) MACS Read/write 0136h Unchanged
Second Operand OP2 Read/write 0138h Unchanged
Result Low Word ResLo Read/write 013Ah Undefined
Result High Word ResHi Read/write 013Ch Undefined
Sum Extend SumExt Read 013Eh Undefined
Two registers are implemented for both operands, OP1 and OP2, as shown
in Figure 6–3. Operand 1 uses four different addresses to address the same
register. The different address information is decoded and defines the type of
multiplication operation used.
Figure 6–3. Registers of the Hardware Multiplier
Sum Extension Word, SumExt
Operand 1, OP1
15 0
Operand 2, OP2
Result Low Word, ResLo
Result High Word, ResHi
MPY (130h),MPYS (132h)
MAC (134h), MACS(136h)
OP2 (138h)
ResLo (13Ah)
ResHi (13Ch)
SumExt (13Eh)
The multiplication result is located in two word registers: result high (RESHI)
and result low (RESLO). The sum extend register (SumExt) holds the result
sign of a signed operation or the overflow of the multiply and accumulate
(MAC) operation. See Section 6.5.3 for a description of overflow and
underflow when using the MACS operations.
All registers have the least significant bit (LSB) at bit0 and the most significant
bit (MSB) at bit7 (byte data) or bit15 (word data).