Texas Instruments MSP430x1xx - Manual (Page 422)

Flash Memory Data Structure and Operation
C-10
Note:
When the erase cycle is stopped before its normal completion by the hard-
ware, the timing generator is stopped and erasure of the flash memory can
be marginal. An incomplete erasure can be verified. But an erase level of 1
can be inconsistently read as valid when supply voltage, temperature, ac-
cess time (instruction execution, data read), and frequency vary.
C.2.6 Flash Memory Status During Write (Programming)
The flash memory erase bit level is 1. Bits can only be written (programmed)
to a 0-level. Once a bit is programmed, only the erase function can reset it back
to the 1-level. The byte or word 0-level can not be written (programmed) in one
cycle. Any bit can be programmed from 1 to 0 at any time, but not from 0 to 1.
Two slightly different write operations can be performed: write a single byte or
word of data, or write a sequence of bytes or words. A write sequence of bytes
or words can be performed as multiple sequential, or as a segment write. The
segment write is approximately twice as fast as a multiple sequential write al-
gorithm.
The write (program) operation starts with the following sequence:
- Set the correct input clock frequency of the timing generator by selecting
the clock source and predivider.
- Reset the LOCK control bit, if set.
- Watch the BUSY bit. Continue with the next steps only if the BUSY bit is
reset.
- Set the write-control bit WRT when a single byte of word data is to be writ-
ten.
- Set the write WRT and SEGWRT control bits when segment write is cho-
sen to write multiple bytes or words to the flash memory module.
- Writing the data to the selected address starts the timing generator.
The data is written (programmed) while the timing generator proceeds.
Note:
Whenever the write cycle is stopped before its normal ending by the hard-
ware, the timing generator is stopped and the data written to the flash
memory can be marginal. The data may be incorrect, which can be verified,
or the data are verified to be correct but the programming is marginal. Read-
ing of the data may be inconsistently valid when varying the supply voltage,
the temperature, the access time (instruction execution, data read), or the
time.