Texas Instruments MSP430x1xx User Manual

Page 371

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Instruction Set Overview

B-21

Instruction Set Description

* CLRZ

Clear zero bit

Syntax

CLRZ

Operation

0

Z

or
(.NOT.src .AND. dst –> dst)

Emulation

BIC

#2,SR

Description

The constant 02h is inverted (0FFFDh) and logically ANDed with the
destination operand. The result is placed into the destination. The clear zero
bit instruction is a word instruction.

Status Bits

N: Not affected
Z: Reset to 0
C: Not affected
V: Not affected

Mode Bits

OscOff, CPUOff, and GIE are not affected.

Example

The zero bit in the status register is cleared.

CLRZ

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