Texas Instruments MSP430x1xx - Manual (Page 201)

11-25
Timer_B
11.5.2 Output Control Block
The output control block prepares the value of the OUTx signal, which is
latched into the OUTx flip-flop with the next positive timer clock edge, as shown
in Figure 11–23 and Table 11–3. The equal signals EQUx and EQU0 are
sampled during the negative level of the timer clock, as shown in Figure 11–23.
Figure 11–23.Output Control Block
The timer is Incremented with the rising edge of the timer clock.
Timer
Clock
Timer
TBR
EQUx
EQU0
EQU0, Delayed
Used in Up Mode Only
TBR = n
TBCLx = n
n–2 n–1 n n+1
TBR(max)
or TBCL0
0 1
TBR = 0
or
TBR = TBCL0
EQU0 delayed is used in up mode, not EQU0. EQU0 is active high when
TBR = TBCL0. EQU0 delayed is active high when TBR = 0.
D Q
Reset
POR
OUTx
Set
Timer Clock
OUTx
OUTx Signal
EQU0
EQUx
OMx2 OMx1 OMx0
Output
Control
Block