Texas Instruments MSP430x1xx - Manual (Page 426)

Flash Memory Control Registers
C-14
ment write mode, the control register can be written if wait mode is active
(WAIT=1). In an active segment write mode and while WAIT=0, writing to con-
trol register FCTL1 will also end in an access violation with ACCVIFG=1.
Read access is possible at any time without restrictions.
The control bits of control register FCTL1 are:
7 0
rw–0 rw–0 r0 r0 r0 rw–0 rw–0 r0
0128h
FCTL1
15 8
FCTL1 read:
FCTL1 write: 0 9 6 h
0 A 5 h
Erase MEras
SEG
WRT
WRT res. res. res. res.
Erase 0128h, bit1, Erase a segment
0: No segment erase is started.
1: Erase of one segment is enabled. The segment n to be erased is
defined by a
dummy write into any address within the segment.
The Erase bit is automatically reset when the erase operation is
completed.
Note: Instruction fetch access during erase is allowed. Any other
access to the flash memory during erase results in setting the
ACCVIFG bit, and an NMI interrupt is requested. The NMI
interrupt routine should handle such violations.
MEras 0128h, bit2, Mass-erase, Segment0 to Segmentn are erased together.
0: No erase is started
1: Erase of Segment0 to Segmentn is enabled. When a dummy write
into any address in Segment0 to Segmentn is executed, mass-
erase is started. The MEras bit is automatically reset when the
erase operation is completed.
Note: Instruction fetch access during mass-erase is allowed. Any other
access to the flash memory during erase results in setting the
ACCVIFG bit, and an NMI interrupt is requested. The NMI
interrupt routine should handle such violations.
WRT 0128h, bit6, The bit WRT should be set to get a successful write execution.
If bit WRT is reset and write access to the flash memory is performed,
an access violation occurs and ACCVIFG is set.
Note: Instruction fetch access during erase is allowed. Any other
access to the flash memory during erase results in setting the
ACCVIFG bit, and an NMI interrupt is requested. The NMI
interrupt routine should handle such violations.
SEGWRT 0128h, bit7, Bit SEGWRT can be used to reduce total programming time.
The segment-write bit SEGWRT is useful if larger sequences of data
have to be programmed. If programming of one segment is completed,
a reset and set sequence should be performed to enable access to the
next segment. The WAIT bit should be high before the next write
instruction is executed. See also paragraph C.1.1 and Figure C–9.
0: No segment write accelerate is selected.
1: Segment write is used. This bit needs to be reset and set between
segment borders.