Texas Instruments MSP430x1xx - Manual (Page 136)

The Watchdog Timer
9-4
Bit 5: The NMI bit selects the function of the RST/NMI input pin. It is
cleared by the PUC signal.
NMI = 0:
The RST/NMI input works as reset input.
As long as the RST/NMI pin is held low, the internal
signal is active (level sensitive).
NMI = 1: The RST/NMI input works as an edge-sensitive non-
maskable interrupt input.
Bit 6: If the NMI function is selected, this bit selects the activating edge
of the RST/NMI input. It is cleared by the PUC signal.
NMIES = 0: A rising edge triggers an NMI interrupt.
NMIES = 1: A falling edge triggers an NMI interrupt.
CAUTION:
Changing the NMIES bit with software can generate
an NMI interrupt.
Bit 7: This bit stops the operation of the watchdog counter. The clock
multiplexer is disabled and the counter stops incrementing. It holds
the last value until the hold bit is reset and the operation continues.
It is cleared by the PUC signal.
HOLD = 0:
The WDT is fully active.
HOLD = 1: The clock multiplexer and counter are stopped.
9.1.1.1 Accessing the WDTCTL (Watchdog Timer Control Register)
The WDTCTL register can be read or written to. As illustrated in Figure 9–3,
WDTCTL can be read without the use of a password. A read access is
performed by accessing word address 0120h. The low byte contains the value
of WDTCTL. The value of the high byte is always read as 069h.
Figure 9–3. Reading WDTCTL
0
15 0
r
WDTCTL
0120h
Read Data
rw-x, (w)
1 1 0 1 0 0 1
7 8
r r r r r r r
6 9
Write access to WDTCTL, illustrated in Figure 9–4, is only possible using the
correct high-byte password. To change register WDTCTL, write to word
address 0120h. The low byte contains the data to write to WDTCTL. The high
byte is the password, which is 05Ah. A system reset (PUC) is generated if any
value other than 05Ah is written to the high byte of address 0120h.
Figure 9–4. Writing to WDTCTL
0
15 0
(w)
WDTCTL
0120h
Write Data
rw-x, (w)
1 0 1 1 0 1 0
7 8
5 A
(w) (w) (w) (w) (w) (w) (w)