Texas Instruments MSP430x1xx User Manual

Page 421

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Flash Memory Data Structure and Operation

C-9

Flash Memory

The

dummy write starts the erase cycle. An example of dummy write is

CLR &0F012h.

Note that a dummy write is ignored in a segment where the selected operation
can not be executed successfully.

An example of such a situation can take place when Segment 1 is to be erased:
the control bits are set properly, but the

dummy write is sent to the information

memory. No flag indicates this unsuccessful erase situation.

Figure C–7.Basic Flash EEPROM Module Timing During the Erase Cycle

BUSY

Generate

Erase Voltage

Erase Operation Active

Entire Erase Cycle Timing

Erase Voltage

Remove

Time of Increased Current Consumption From Supply, VCC

Mass Erase: t

(erase)

= 5296/fx; Page Erase: t

(erase)

= 4817/fx

The erase cycle completes successfully when none of the following restric-
tions is violated:

-

The selected clock source is available until the cycle is completed.

-

The predivider should not be modified during the operation.

-

No further access to the flash memory module is performed while BUSY
is set.

J

No read of data from this block

J

No write into this block

J

No further erase of this block

An access will result in setting the KEYV bit and requesting an NMI inter-
rupt. The NMI interrupt routine should handle such violations.

-

The supply voltage should be within the devices’ electrical specifications
defined in the respective data sheet; however, slight variations can be tol-
erated.

Control bit BUSY indicates an active erase cycle. It is set immediately after a
dummy write starts the timing generator. It remains set until the entire erase
cycle is completed and the erased segment or block is ready to be accessed
again. The BUSY bit can not be set by software. But it can be reset. In case
of emergency, set the emergency exit (EMEX) bit and the erase operation will
be stopped immediately; BUSY bit is reset. One example of stop erase by soft-
ware is when the supply voltage drops drastically and the operating conditions
of the controller are exceeded. Another example is when the timing of the
erase cycle gets out of control, for example, when the clock-source signal is
lost.

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