Texas Instruments MSP430x1xx User Manual
Page 81
Instruction Set Overview
5-17
16-Bit CPU
5.3
Instruction Set Overview
This section gives a short overview of the instruction set. The addressing
modes are described in Section 5.2.
Instructions are either single or dual operand or jump.
The source and destination parts of an instruction are defined by the following
fields:
src
The source operand defined by As and S-reg
dst
The destination operand defined by Ad and D-reg
As
The addressing bits responsible for the addressing mode used
for the source (src)
S-reg
The working register used for the source (src)
Ad
The addressing bits responsible for the addressing mode used
for the destination (dst)
D-reg
The working register used for the destination (dst)
B/W
Byte or word operation:
0: word operation
1: byte operation
Note:
Destination Address
Destination addresses are valid anywhere in the memory map. However,
when using an instruction that modifies the contents of the destination, the
user must ensure the destination address is writeable. For example, a
masked-ROM location would be a valid destination address, but the contents
are not modifiable, so the results of the instruction would be lost.