Texas Instruments MSP430x1xx - Manual (Page 298)

Conversion Memory
15-8
15.4 Conversion Memory
A typical approach in single-channel converters uses an interrupt request to
signal the end of the conversion and requires the conversion data to be moved
to another location before another conversion can be performed. However, the
ADC12 incorporates 16 conversion-memory registers (ADC12MEMx, see
Figure 15–1) allowing the A/D converter to run multiple conversions without
software intervention. This increases the system performance by reducing
software overhead.
Additionally, each of the 16 conversion-memory registers has an associated
control register (ADC12MCTLx) allowing total flexibility for each conversion.
The memory-control registers allow the user to specify the channel and
reference(s) used for each individual conversion. All other control bits that
configure the other operating conditions of the ADC12, such as conversion
modes, sample and conversion control signal, ADC clock, and sample timing,
are located in control registers ADC12CTL0 and ADC12CTL1. Each
conversion-memory register is individually accessible by software in the
address range 0140h – 015Eh.
Using the conversion memory involves control bits in two places. First, the
CStartAdd bits located in ADC12CTL1 point to the conversion-memory
register to be used for single-channel conversions or the first
conversion-memory register to be used for a sequence. The conversion-start
address (CStartAdd) can be any value from 0h – 0Fh and points to
ADC12MEM0 – ADC12MEM15, respectively. Second, the end-of-sequence
(EOS) bit in each conversion-memory control register marks the end of an
automatic-conversion sequence.
The EOS bit, when set, defines the end of a conversion sequence. When
cleared, an internal conversion-memory pointer (not visible to software) is in-
cremented after the current conversion is completed and the conversion result
is stored in the conversion memory. The conversion-memory pointer is then
prepared to use the next conversion-memory register to store the results of the
next conversion. The internal conversion-memory pointer is incremented with
each conversion until a set EOS bit is encountered. Note that defining the end
of a sequence is independent from defining the mode of operation (see the
Conversion Modes section), and that the EOS bits are ignored when using
single-conversion mode or repeated conversion of a single-channel mode.
Conversion sequences always use sequential conversion-memory registers,
can start with any conversion-memory register, and do not necessarily require
any EOS bit to be set. For example, if the CONSEQ bits define the mode of
operation to be conversion of a sequence (single or repeated), the CStartAdd
bits point to conversion-memory register 14, and no EOS bits are set for any
of the conversion-memory registers, then the conversion-memory registers
will be used in sequential order (14, 15, 0, 1, 2, ... , 14, 15, 0, 1, 2,
…
etc.) for
each consecutive conversion, and the sequence of conversions will continue
until stopped by software. This is useful, for example, in an application that
must take advantage of the buffering supplied by the conversion memory but
requires more than 16 repeated conversions of a single channel. In this
instance the user should set up each memory-control register identically,
specifying the same channel and reference(s) for each conversion, and all
EOS bits must be cleared. Once the converter is started, it will continue to run
until stopped by software.