Texas Instruments MSP430x1xx - Manual (Page 237)

Control and Status Registers
12-21
USART Peripheral Interface, UART Mode
The timing of the running bit is expanded by one clock cycle of the baud-rate-
divider input clock if bit m
i
is set.
Each time a bit is received or transmitted, the next bit in the modulation control
register determines the present bit timing. The first bit time in the protocol—the
start bit time—is determined by UBR plus m0; the next bit is determined by
UBR plus m1, and so on.
The modulation sequence is:
m0 – m1 – m2 – m3 – m4 – m5 – m6 – m7 – m0 – m1 – m2 – .....
12.5.5 Receive-Data Buffer URXBUF
The receive-data buffer (URXBUF), shown in Figure 12–21, contains previous
data from the receiver shift register. Reading URXBUF resets the receive-error
bits, the RXWake bit, and the interrupt flag (URXIFG).
Figure 12–21. USART0 Receive Data Buffer URXBUF
27
7 0
URXBUF0, 076h
26 25 24 23 22 21 20
r r r r r r r r
URXBUF1, 07Eh
In seven-bit length mode, the MSB of the URXBUF is always reset.
The receive data buffer is loaded with the recently-received character as
described in Table 12–5, when receive and control conditions are true.
Table 12–5.Receive Data Buffer Characters
URXEIE URXWIE Load URXBUF With: PE FE BRK
0 1 Error-free address characters 0 0 0
1 1 All address characters X X X
0 0 Error-free characters 0 0 0
1 0 All characters X X X
12.5.6 Transmit Data Buffer UTXBUF
The transmit data buffer (UTXBUF), shown in Figure 12–22, contains current
data to be transmitted.
Figure 12–22. Transmit Data Buffer UTXBUF
27
7 0
UTXBUF0, 077h
26 25 24 23 22 21 20
rw rw rw rw rw rw rw rw
UTXBUF1, 07Fh
The UTXIFG flag indicates that the UTXBUF buffer is ready to accept another
character for transmission.
The transmission is initialized by writing data to UTXBUF. The transmission of
this data is started immediately if the transmitter shift register is empty or is
going to be empty.