Texas Instruments MSP430x1xx - Manual (Page 225)

Asynchronous Operation
12-9
USART Peripheral Interface, UART Mode
The following procedure sends out an idle frame to identify an address
character:
1) Set the TXWake bit and then write any word (don’t care) to the UTXBUF
(UTXIFG must be set).
When the transmitter shift register is empty, the contents of UTXBUF are
shifted to the transmit shift register and the TXWake value is shifted to
WUT.
2) Set bit WUT, which suppresses the start, data, and parity bits and
transmits an idle period of exactly 11 bits, as shown in Figure 12–10.
The next data word, shifted out of the serial port after the address-
character identifying idle period, is the second word written to the UTXBUF
after the TXWake bit has been set. The first data word written is
suppressed while the address identifier is sent out and ignored thereafter.
Writing the first don’t care word to UTXBUF is necessary to shift the
TXWAKE bit to WUT and generate an idle-line condition.
Figure 12–10. USART Transmitter Idle Generation
11-Bit Idle Period
Mark
Space
XXXX SP ST XXXXXXX
Example: One Stop Bit
11-Bit Idle Period
Mark
Space
XXXX SP ST XXXXXXX
Example: Two Stop Bits
SP
SP: Stop Bit
ST: Start Bit
12.3.5 Address - Bit Multiprocessor Format
In the address-bit multiprocessor format shown in Figure 12–11, characters
contain an extra bit used as an address indicator. The first character in a block
of data carries an address bit which indicates that the character is an address.
The RXWake bit is set when a received character is an address character. It
is transferred into the receive buffer (receive conditions are true).
Usually, if the USART URXWIE bit is set, data characters are assembled by
the receiver but are not transferred to the receiver buffer URXBUF, nor are
interrupts generated. When a character that has an address bit set is received,
the receiver is temporarily activated to transfer the character to URXBUF and
to set the URXIFG. Error status flags are set as applicable. The application
software processes the succeeding operation to optimize resource handling
or reduce current consumption. The application software can validate the
received address. If there is a match, the processor can read the remainder
of the data block. If there is not a match, the processor waits for the next
address character to arrive.