Texas Instruments MSP430x1xx User Manual
Page 329
ADC12 Control Registers
15-39
ADC12
15.8.5.1 ADC Interrupt Vector Register, Software Example
The following software example shows the use of vector word ADC12IV and
the associated software overhead. The numbers at the right margin show the
cycles required for every instruction. The example shows a basic interrupt
handler structure that can be adopted to individual application requirements.
The software overhead for the different interrupt sources, including interrupt
latency and return-from-interrupt cycles (but not the task handling itself), is:
-
ADC12IFG.0 to ADC12IFG.14, ADC12OV
16 cycles
-
ADC12IFG.15
14 cycles
; Interrupt handler for the 12-bit ADC.
; The flag, which is enabled and has the highest priority,
; determines the interrupt vector word and is reset by
; hardware after accessing (instruction
; ADD &TADC12IV,PC). Flags ADC12OV, ADC12TOV, and
; ADC12IFG.x are reset by hardware.
ADC_HND
$
; Interrupt latency
6
ADD &ADC12IV,PC
; Add offset to Jump table
3
RETI
; Vector 0: No interrupt
5
JMP ADC12OV
; Vector 2: ADC overflow
2
JMP ADC12TOV
; Vector 4: ADC timing overflow
2
JMP ADC12MOD0
; Vector 6: ADC12MEM0 was loaded
; (ADC12IFG.0)
2
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JMP ADC12MOD1
; Vector 8: ADC12MEM1 was loaded
; (ADC12IFG.1)
2
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:
:
JMP ADC12MOD13
; Vector 34: ADC12MEM14 was loaded
; (ADC12IFG.14)
2
JMP ADC12MOD14
; Vector 36: ADC12MEM15 was loaded
; (ADC12IFG.15)
2
;
; Module 15. Handler for ADC12IFG.15 starts here. Note a JMP
; instruction is not needed to get here because the PC is
; already here after the ADD&ADC12IV,PC instruction.
;
ADC12OV
...
; Vector 2: ADC12OV Flag
...
; First instruction to handle ADC12
; overflow condition
RETI
5
;
ADC12TOV
...
; Vector 4: ADC12OV Flag
...
; First instruction to handle ADC12 timing
; overflow condition
RETI
5
;
ADC12MOD2
; Vector 10: ADC12MEM2 was loaded
; (ADC12IFG.2)
MOV &ADC12MEM2,R6 ; ADC12IFG2 is reset due to access
; of ADC memory
...
; Task starts here