Texas Instruments MSP430x1xx - Manual (Page 166)

Timer_A Registers
10-26
Table 10–5.Input Clock Divider Control Bits
ID1 ID0 Operation Description
0 0 /1 Input clock source is passed to the timer.
0 1 /2 Input clock source is divided by two.
1 0 /4 Input clock source is divided by four.
1 1 /8 Input clock source is divided by eight.
Bits 8, 9: Clock source selection bits. Table 10–6 describes the clock source
selections.
Table 10–6.Clock Source Selection
SSEL1 SSEL0 O/P Signal Comment
0 0 TACLK See data sheet device description.
0 1 ACLK Auxiliary clock ACLK is used.
1 0 SMCLK System clock SMCLK.
1 1 INCLK See device description in data sheet.
Bits 10 to 15: Unused
Note: Changing Timer_A Control Bits
If the timer operation is modified by the control bits in the TACTL register, the
timer should be halted during this modification. Critical modifications are the
input select bits, input divider bits, and the timer clear bit. Asynchronous
clocks, input clock, and system clock can result in race conditions where the
timer reacts unpredictably.
The recommended instruction flow is:
1) Modify the control register and stop the timer.
2) Start the timer operation.
For example:
MOV #01C6,&TACTL ; ACLK/8, timer stopped, timer cleared
BIS #10h,&TACTL ; Start timer with up mode
10.6.2 Timer_A Register TAR
The TAR register is the value of the timer.
Figure 10–28. TAR Register
rw-(0)
15 0
TAR
170h
Timer Value
rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) rw-(0)rw-(0)rw-(0)rw-(0)rw-(0) rw-(0) rw-(0)rw-(0) rw-(0) rw-(0)